AD2S90 Просмотр технического описания (PDF) - Analog Devices

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AD2S90

Low Cost, Complete 12-Bit Resolver-to-Digital Converter

Analog Devices 

AD2S90

TMS32020 Interfacing

Figure 11 shows the serial interface between the AD2S90 and

the TMS32020. The interface is configured in alternate internal

framing, external clock (externally inverted) mode. Sixteen bits

of data are clocked from the AD2S90 into the data receive regis-

ter (DRR) of the TMS32020. The DRR is fixed at 16 bits. To

obtain the 12-significant bits, the processor needs to execute

three right shifts. (First bit read is void, the last three will be

zeros). When 16 bits have been received by the TMS32020, it

generates an internal interrupt to read the data from the DRR.

Select the AD2S90 and frame the data. The S1 register is fixed

at 16 bits, therefore, to obtain the 12-significant bits the proces-

sor needs to execute four right shifts. Once the NEC7720 has

read 16 bits, an internal interrupt is generated to read the inter-

nal contents of the S1 register.

SCLK

␮PD7720

SIEN

S1

SCLK

AD2S90

CS

DATA

SCLK

TMS32020

FSR

DRR

SCLK

AD2S90

CS

DATA

NOTE:

ADDITIONAL PINS OMITTED FOR CLARITY

Figure 11. TMS32020/AD2S90 Serial Interface

DSP56000 Interface

Figure 12 shows a serial interface between the AD2S90 and the

DSP56000. The DSP in configured for normal mode synchro-

nous operation with gated clock with SCLK and SC1 as out-

puts. SC1 is applied to CS.

SCLK

DSP56000

SC1

SRD

SCLK

AD2S90

CS

DATA

NOTE:

ADDITIONAL PINS OMITTED FOR CLARITY

Figure 13. µPD7720/AD2S90 Serial Interface

EDGE TRIGGERED 4؋ DECODING LOGIC

In most data acquisition or control systems the A, B incremental

outputs must be decoded into absolute information, normally a

parallel word, before they can be utilized effectively.

To decode the A, B outputs on the AD2S90 the user must

implement a 4× decoding architecture. The principle states that

one A, B cycle represents 4 LSB weighted increments of the

converter (see Equation 4).

Up = (↑A) • B + (↓B) • A + (↓A) • B + (↑Β) • A

Down = (↑A) • B + (↑B) • A + (↓A) • B + (↓B) • A

(4)

CH A

CLOCKWISE ROTATION

COUNTER CLOCKWISE ROTATION

NOTE:

ADDITIONAL PINS OMITTED FOR CLARITY

Figure 12. DSP56000/AD2S90 Serial Interface

The DSP56000 assumes valid data on the first falling edge of

SCLK. SCLK is inverted to ensure that the valid data is clocked

in after one leading bit. The receive data shift register (SRD) is

set for a 13-bit word.

When this register has received 13 bits of data, it generates an

internal interrupt on the DSP56000 to read the 12 bits of sig-

nificant data from the register.

NEC7720 Interface

Figure 13 shows the serial interface between the NEC7720 and

the AD2S90. The NEC7720 expects data on the rising edge of

its SCLK output, and therefore unlike the previous interfaces no

inverter is required to clock data into the S1 register. There is

no need to ignore the first data bit read. SIEN is used to Chip

CH B

UP

DOWN

Figure 14. Principles of 4× Decoding

The algorithms in Equation 4 can be implemented using the

architecture shown in Figure 15. Traditionally the direction of

the shaft is decoded by determining whether A leads B. The

AD2S90 removes the need to derive direction by supplying a

direction output state which can be fed straight into the up-

down counter.

For further information on this topic please refer to the applica-

tion note “Circuit Applications of the AD2S90 Resolver-to-

Digital Converters.”

CHA

CHB

A

A

EDGE GENERATOR B

B

DIRECTION

CLOCK

U/D

UP/DOWN

COUNTER

RESET

PARALLEL

DIGITAL

OUTPUT

Figure 15. 4× Decoding Incremental to Parallel Conversion

–8–

REV. D

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