MACH120-18 Просмотр технического описания (PDF) - Lattice Semiconductor

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производитель

MACH120-18

High-Performance EE CMOS Programmable Logic

Lattice Semiconductor 

CONNECTION DIAGRAM

Top View

Block A

PLCC

Block D

I/O7

I/O8

I/O9

I/O10

I/O11

CLK0/I0

CLK1/I1

I2

VCC

GND

I3

I/O12

I/O13

I/O14

I/O15

I/O16

I/O17

9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61

10

60

11

59

12

58

13

57

14

56

15

55

16

54

17

53

18

52

19

51

20

50

21

49

22

48

23

47

24

46

25

45

26

44

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

I/O41

I/O40

I/O39

I/O38

I/O37

I/O36

I7

GND

VCC

I6

CLK3/I5

CLK2/I4

I/O35

I/O34

I/O33

I/O32

I/O31

Block B

Note:

Pin-compatible with the MACH220 and MACH221.

PIN DESIGNATIONS

CLK/I = Clock or Input

GND = Ground

I

= Input

I/O = Input/Output

VCC = Supply Voltage

Block C

14129J-2

4

MACH120-12/15

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