T0
CLK
ADVANCE
64Mb: x16, x32
SYNCFLASH MEMORY
Figure 7
Consecutive Read Bursts
T1
T2
T3
T4
T5
COMMAND
READ
NOP
NOP
ADDRESS
BANK,
COL n
NOP
READ
NOP
X = 0 cycles
BANK,
COL b
DQ
DOUT
n
CAS Latency = 1
DOUT
n+1
DOUT
n+2
DOUT
n+3
DOUT
b
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
READ
NOP
NOP
NOP
READ
NOP
NOP
ADDRESS
BANK,
COL n
X = 1 cycle
BANK,
COL b
DQ
DOUT
n
DOUT
n+1
DOUT
n+2
DOUT
n+3
DOUT
b
CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
READ
NOP
NOP
NOP
READ
NOP
NOP
NOP
ADDRESS
BANK,
COL n
BANK,
COL b
X = 2 cycles
DQ
DOUT
n
DOUT
n+1
DOUT
n+2
CAS Latency = 3
NOTE: Each READ command may be to either bank. DQM is LOW.
DOUT
n+3
DOUT
b
DON’T CARE
64Mb: x16, x32 SyncFlash
MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02
20
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©2002, Micron Technology, Inc.