LXT971A Просмотр технического описания (PDF) - Intel

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LXT971A

3.3V Dual-Speed Fast Ethernet PHY Transceiver

Intel 

LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver

Table 58. Transmit Control Register (Address 30)

Bit

Name

Description

30.15:11 Reserved

Ignore

30.12

Transmit Low Power

1 = Forces the transmitter into low power mode.

Also forces a zero-differential transmission.

0 = Normal transmission.

30.11:10

Port Rise Time Control1

00 = 3.0 ns (default = TXSLEW<1:0> pins)

01 = 3.4 ns

10 = 3.9 ns

11 = 4.4 ns

30.9:0 Reserved

Ignore

1. Values are relative approximations. Not guaranteed or production tested.

2. R/W = Read/Write

Type2

R/W

Default

0

R/W

0

R/W

00

R/W

0

Datasheet

87

Document #: 249414

Revision #: 002

Rev. Date: August 7, 2002

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