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LTC6990I

TimerBlox: Voltage Controlled Silicon Oscillator

Linear Technology 

LTC6990

APPLICATIONS INFORMATION

SUPPLY BYPASSING AND PCB LAYOUT GUIDELINES

The LTC6990 is a 2.2% accurate silicon oscillator when

used in the appropriate manner. The part is simple to use

and by following a few rules, the expected performance

is easily achieved. The most important use issues involve

adequate supply bypassing and proper PCB layout.

Figure 17 shows example PCB layouts for both the SOT-23

and DCB packages using 0603 sized passive components.

The layouts assume a two layer board with a ground plane

layer beneath and around the LTC6990. These layouts are

a guide and need not be followed exactly.

1. Connect the bypass capacitor, C1, directly to the V+ and

GND pins using a low inductance path. The connection

from C1 to the V+ pin is easily done directly on the top

layer. For the DCB package, C1’s connection to GND is

also simply done on the top layer. For the SOT-23, OUT

can be routed through the C1 pads to allow a good C1

GND connection. If the PCB design rules do not allow

that, C1’s GND connection can be accomplished through

multiple vias to the ground plane. Multiple vias for both

the GND pin connection to the ground plane and the

C1 connection to the ground plane are recommended

to minimize the inductance. Capacitor C1 should be a

0.1µF ceramic capacitor.

2. Place all passive components on the top side of the

board. This minimizes trace inductance.

3. Place RSET as close as possible to the SET pin and

make a direct, short connection. The SET pin is a

current summing node and currents injected into this

pin directly modulate the operating frequency. Having

a short connection minimizes the exposure to signal

pickup.

4. Connect RSET directly to the GND pin. Using a long path

or vias to the ground plane will not have a significant

affect on accuracy, but the direct, short connection is

recommended and easy to apply.

5. Use a ground trace to shield the SET pin. This provides

another layer of protection from radiated signals.

6. Place R1 and R2 close to the DIV pin. A direct, short

connection to the DIV pin minimizes the external signal

coupling.

V+

R1

R2

C1

V+

DIV

SET

RSET

OE

OUT

LTC6990

GND

V+

SET

DIV

RSET

C1

0.1µF

V+

R1

R2

C1

V+

OUT

OE

OUT

GND

GND

V+

OE

SET

DIV

R1

RSET

R2

DCB PACKAGE

TSOT-23 PACKAGE

6990 F17

Figure 17. Supply Bypassing and PCB Layout

For more information www.linear.com/LTC6990

6990fc

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