LTC2184CUPPBF Просмотр технического описания (PDF) - Linear Technology
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LTC2184CUPPBF Datasheet PDF : 36 Pages
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LTC2185/LTC2184/LTC2183
Power Requirements The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 9)
LTC2185
LTC2184
LTC2183
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
CMOS Output Modes: Full Data Rate and Double Data Rate
VDD
OVDD
IVDD
Analog Supply Voltage
Output Supply Voltage
Analog Supply Current
(Note 10)
(Note 10)
DC Input
Sine Wave Input
l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9
V
l 1.1 1.8 1.9 1.1 1.8 1.9 1.1 1.8 1.9
V
l
206 228
209
171 188
173
111 124
mA
113
mA
IOVDD Digital Supply Current Sine Wave Input, OVDD = 1.2V
10
8
6
mA
PDISS Power Dissipation
DC Input
l
Sine Wave Input, OVDD = 1.2V
370 410
388
308 339
321
200 223 mW
211
mW
LVDS Output Mode
VDD
Analog Supply Voltage (Note 10)
l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9
V
OVDD Output Supply Voltage (Note 10)
l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9
V
IVDD
Analog Supply Current Sine Input, 1.75mA Mode
Sine Input, 3.5mA Mode
l
211
213 233
175
177 193
115
mA
117 128
mA
IOVDD Digital Supply Current Sine Input, 1.75mA Mode
(0VDD = 1.8V)
Sine Input, 3.5mA Mode
l
PDISS Power Dissipation
Sine Input, 1.75mA Mode
Sine Input, 3.5mA Mode
l
40
76 86
452
520 574
40
75 85
387
454 500
39
mA
75 84
mA
277
mW
346 382 mW
All Output Modes
PSLEEP Sleep Mode Power
1
1
1
mW
PNAP Nap Mode Power
16
16
16
mW
PDIFFCLK Power Increase with Differential Encode Mode Enabled
20
20
20
mW
(No increase for Nap or Sleep Modes)
Timing Characteristics The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
LTC2185
LTC2184
LTC2183
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
fS
Sampling Frequency (Note 10)
l1
125 1
105 1
80 MHz
tL
ENC Low Time (Note 8) Duty Cycle Stabilizer Off l 3.8 4 500 4.52 4.76 500 5.93 6.25 500
ns
Duty Cycle Stabilizer On l 2
4 500 2 4.76 500 2 6.25 500
ns
tH
ENC High Time (Note 8) Duty Cycle Stabilizer Off l 3.8 4 500 4.52 4.76 500 5.93 6.25 500
ns
Duty Cycle Stabilizer On l 2
4 500 2 4.76 500 2 6.25 500
ns
tAP
Sample-and-Hold
Acquisition Delay Time
0
0
0
ns
SYMBOL PARAMETER
CONDITIONS
Digital Data Outputs (CMOS Modes: Full Data Rate and Double Data Rate)
tD
tC
tSKEW
ENC to Data Delay
ENC to CLKOUT Delay
DATA to CLKOUT Skew
Pipeline Latency
CL = 5pF (Note 8)
CL = 5pF (Note 8)
tD – tC (Note 8)
Full Data Rate Mode
Double Data Rate Mode
MIN
TYP
MAX
UNITS
l
1.1
1.7
3.1
ns
l
1
1.4
2.6
ns
l
0
0.3
0.6
ns
6
Cycles
6.5
Cycles
218543f
7
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