LTC4365CDDBTRMPBF Просмотр технического описания (PDF) - Linear Technology

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LTC4365CDDBTRMPBF

UV, OV and Reverse Supply Protection Controller

Linear Technology 

LTC4365

APPLICATIONS INFORMATION

Transients During OV Fault

The circuit of Figure 14 was used to display transients

during an overvoltage condition. The nominal input supply

is 24V and it has an overvoltage threshold of 30V. The

parasitic inductance is that of a 1 foot wire (roughly 300nH).

Figure 15 shows the waveforms during an overvoltage

condition at VIN. These transients depend on the parasitic

inductance and resistance of the wire along with the ca-

pacitance at the VIN node. D1 is an optional power clamp

(TVS, Tranzorb) recommended for applications where

the DC input voltage can exceed 24V and with large VIN

parasitic inductance. No clamp was used to capture the

waveforms of Figure 15. In order to maintain reverse supply

protection, D1 must be a bi-directional clamp rated for at

least 225W peak pulse power dissipation.

12 INCH WIRE

VIN

24V +

LENGTH

CIN

1000μF

SI9945

60V

M1

M2

VOUT

+

COUT

100μF

9Ω

D1

OPTIONAL

R3

100k

GATE

VIN

VOUT

LTC4365

SHDN

R2

2370k

R1

40.2k

UV

FAULT

OV

GND

OV = 30V

4365 F14

Figure 14. OV Fault with Large VIN Inductance

GATE

VOUT

20V/DIV

VOUT

GATE

GND

VIN

20V/DIV

GND

IIN

2A/DIV

0A

250ns/DIV

4365 F15

Figure 15. Transients During OV Fault When No

Tranzorb (TVS) Is Used

14

MOSFET Selection

To protect against a negative voltage at VIN, the external

N-channel MOSFETs must be configured in a back-to-

back arrangement. Dual N-channel packages are thus the

best choice. The MOSFET is selected based on its power

handling capability, drain and gate breakdown voltages,

and threshold voltage.

The drain to source breakdown voltage must be higher

than the maximum voltage expected between VIN and

VOUT. Note that if an application generates high energy

transients during normal operation or during Hot Swap™,

the external MOSFET must be able to withstand this

transient voltage.

Due to the high impedance nature of the charge pump that

drives the GATE pin, the total leakage on the GATE pin must

be kept low. The gate drive curves of Figure 2 were measured

with a 1μA load on the GATE pin. Therefore, the leakage

on the GATE pin must be no greater than 1μA in order to

match the curves of Figure 2. Higher leakage currents will

result in lower gate drive. The dual N-channel MOSFETs

shown in Table 1 all have a maximum GATE leakage cur-

rent of 100nA. Additionally, Table 1 lists representative

MOSFETs that would work at different values of VIN.

Layout Considerations

The trace length between the VIN pin and the drain of the

external MOSFET should be minimized, as well as the

trace length between the GATE pin of the LTC4365 and

the gates of the external MOSFETs.

Place the bypass capacitors at VOUT as close as possible

to the external MOSFET. Use high frequency ceramic

capacitors in addition to bulk capacitors to mitigate Hot

Swap ringing. Place the high frequency capacitors closest

to the MOSFET. Note that bulk capacitors mitigate ringing

by virtue of their ESR. Ceramic capacitors have low ESR

and can thus ring near their resonant frequency.

4365f

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