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LTC1409CSW

12-Bit, 800ksps Sampling A/D Converter with Shutdown

Linear Technology 

LTC1409

APPLICATI S I FOR ATIO

NAP/SLP

t3

SHDN

LTC1409 • F14a

Figure 14a. NAP/SLP to SHDN Timing

SHDN

t4

CONVST

LTC1409 • F14b

Figure 14b. SHDN to CONVST Wake-Up Timing

CS

t2

CONVST

t1

RD

LTC1409 • F15

Figure 15. CS to CONVST Setup Timing

can be latched with the BUSY rising edge. Mode 1a shows

operation with a narrow logic low CONVST pulse. Mode 1b

shows a narrow logic high CONVST pulse.

In mode 2 (Figure 18) CS is tied low. The falling edge of

CONVST signal again starts the conversion. Data outputs

are in three-state until read by the MPU with the RD signal.

Mode 2 can be used for operation with a shared MPU

databus.

In slow memory and ROM modes (Figures 19 and 20) CS

is tied low and CONVST and RD are tied together. The MPU

starts the conversion and reads the output with the RD

signal. Conversions are started by the MPU or DSP (no

external sample clock).

In slow memory mode the processor applies a logic low to

RD (= CONVST) starting the conversion. BUSY goes low

forcing the processor into a WAIT state. The previous

conversion result appears on the data outputs. When the

conversion is complete, the new conversion results ap-

pear on the data outputs; BUSY goes high releasing the

processor, and the processor takes RD (= CONVST) back

high and reads the new conversion data.

In ROM mode, the processor takes RD (= CONVST) low,

starting a conversion and reading the previous conversion

result. After the conversion is complete, the processor can

read the new result and initiate another conversion.

tCONV

t5

CONVST

t6

t8

BUSY

DATA

DATA (N – 1)

DB11 TO DB0

t7

DATA N

DB11 TO DB0

DATA (N + 1)

DB11 TO DB0

LTC1409 • F16

Figure 16. Mode 1a. CONVST Starts a Conversion. Data Outputs Always Enabled

(CONVST =

)

18

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