K8P2716UZC
Rev. 1.0
datasheet NOR FLASH MEMORY
9.0 COMMAND DEFINITIONS
The K8P2716UZB operates by selecting and executing its operational modes. Each operational mode has its own command set. In order to select a cer-
tain mode, a proper command with specific address and data sequences must be written into the command register. Writing incorrect information which
include address and data or writing an improper command will reset the device to the read mode. The defined valid register command sequences are
stated in Table 5.
[Table 5] Command Sequences (x16)
Command Sequence
Cycle
1st Cycle
2nd Cycle
3rd Cycle
4th Cycle
5th Cycle
6th Cycle
Read
Addr
RA
1
Data
RD
Reset
Addr
1
Data
XXXH
F0H
Addr
Autoselect Manufacturer ID 1), 2)
4
Data
555H
AAH
2AAH
55H
555H
90H
X00H
ECH
Autoselect Device ID1), 2), 3)
Addr
6
Data
555H
AAH
2AAH
55H
555H
90H
X01H
227EH
X0EH
2266H
X0FH
2260H
Addr
Autoselect Block Protect Verify 1), 2)
4
Data
555H
AAH
2AAH
55H
555H
90H
BA / X02H
(See Table 6)
Autoselect Indicator Bit 1), 2)
Addr
4
Data
555H
AAH
2AAH
55H
555H
90H
X03H
(See Table 6)
Addr
Autoselect Master Locking Bit 1), 2)
4
Data
555H
AAH
2AAH
55H
555H
90H
X07H
(See Table 6)
Program
Addr
555H
2AAH
555H
PA
4
Data
AAH
55H
A0H
PD
Write to Buffer 4)
Addr
555H
2AAH
BA
BA
WBL
WBL
6
Data
AAH
55H
25H
WC
PD
PD
Program Buffer to Flash
Addr
BA
1
Data
29H
Write to Buffer Abort Reset 4)
Addr
3
Data
555H
AAH
2AAH
55H
555H
F0H
Unlock Bypass
Addr
3
Data
555H
AAH
2AAH
55H
555H
20H
Unlock Bypass
Program
Addr
2
XXXH
XXXH
PA
Data
A0H
PD
Unlock Bypass
Block Erase
Addr
2
XXXH
XXXH
BA
Data
80H
30H
Unlock Bypass Chip Erase
Addr
2
Data
XXXH
XXXH
80H
XXXH
10H
Unlock Bypass Reset
Addr
2
Data
XXXH
XXXH
90H
XXXH
XXXH
00H
Chip Erase
Addr
6
Data
555H
AAH
2AAH
55H
555H
80H
555H
AAH
2AAH
55H
555H
10H
Block Erase
Addr
555H
2AAH
555H
555H
2AAH
BA
6
Data
AAH
55H
80H
AAH
55H
30H
Block Erase Suspend 5), 6)
Addr
1
Data
XXXH
B0H
Block Erase Resume
Addr
1
Data
XXXH
30H
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