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K4X51163PC Просмотр технического описания (PDF) - Samsung

Номер в каталоге
Компоненты Описание
производитель
K4X51163PC
Samsung
Samsung 
K4X51163PC Datasheet PDF : 23 Pages
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K4X51163PC - L(F)E/G
Mobile-DDR SDRAM
Command Truth Table(V=Valid, X=Dont Care, H=Logic High, L=Logic Low)
COMMAND
CKEn-1 CKEn CS
Register
Refresh
Mode Register Set
H
Auto Refresh
H
Entry
Self
Refresh
Exit
L
Bank Active & Row Addr.
H
Read &
Auto Precharge Disable
Column Address Auto Precharge Enable
H
Write &
Auto Precharge Disable
Column Address Auto Precharge Enable
H
Deep Power Down
Burst Stop
Entry
H
Exit
L
H
Bank Selection
Precharge
H
All Banks
Active Power Down
Entry
H
Exit
L
Precharge Power Down
Entry
H
Exit
L
DM
H
No operation (NOP) : Not defined
H
X
L
H
L
L
L
H
H
X
L
X
L
X
L
L
L
H
H
X
L
X
L
H
L
L
H
X
H
L
L
H
H
L
H
X
L
RAS
L
L
H
X
L
H
H
H
X
H
L
X
V
X
X
H
X
V
X
X
H
CAS
L
L
H
X
H
L
L
H
X
H
H
X
V
X
X
H
X
V
X
H
WE
BA0,1 A10/AP
A12,A11,
A9 ~ A0
Note
L
OP CODE
1, 2
3
H
X
3
H
3
X
X
3
H
V
Row Address
H
V
L
V
L
X
L
Column 4
H
Address
(A0~A9)
4
L
Column 4
H
Address
(A0~A9)
4, 6
X
L
X
7
V
L
L
X
H
X
5
X
V
X
X
X
H
X
X
V
X
8
X
9
X
H
9
Note :
1. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS)
2.EMRS/ MRS can be issued only at all banks precharge state.
A new command can be issued 2 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.
6. During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
7. Burst stop command is valid at every burst length.
8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
February 2006

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