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IDT72V3641

3.3 VOLT CMOS SyncFIFO™ 512 x 36 1,024 x 36 2,048 x 36

Integrated Device Technology 

IDT72V3631/72V3641/72V3651

3.3V CMOS SYNCFIFO™ 512 x 36, 1,024 x 36 and 2,048 x 36

COMMERCIAL TEMPERATURE RANGE

CLKA

CLKB

RST

tRSTS

tFSS

tRSTH

tFSH

FS1,FS0

IR

OR

AE

AF

MBF1,

MBF2

tPIR

tRSF

tRSF

tRSF

0,1

tPOR

tPIR

4658 drw 05

Figure 2. FIFO Reset and Loading X and Y with a Preset Value of Eight

CLKA

4

RST

tFSS

tFSH

FS1,FS0

IR

ENA

A0 - A35

tPIR

tENS1

tENH1

tDS

tDH

AF Offset

(Y)

AE Offset

(X)

NOTE:

1. CSA = LOW, W/RA = HIGH, MBA = LOW. It is not necessary to program Offset register on consecutive clock cycles.

First Word

Stored in FIFO

4658 drw 06

Figure 3. Programming the Almost-Full Flag and Almost-Empty Flag Offset Values from Port A

13

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