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ICS932S208YFLNT

Programmable Timing Control HubTM for Next Gen P4TM Processor

Integrated Device Technology 

ICS932S208

Programmable Timing Control HubTM for Next Gen P4TM Processor

I2C Table: Output Control and Fix Frequency Register

Byte 6

Pin #

Name

Control Function

Bit 7

1,2,7,8,9,12,13,14,

15,18,19,20,22,23,2

6,27,29,31,32,37,38

,40,41,43,44,46,47

Test Clock Mode

Test Clock Mode

Bit 6

-

Bit 5 40,41,43,44,46,47

Bit 4

37,38

Bit 3

Bit 2

7,8,9,12,13,14,15,1

8,19,20,22,23,26,27

,29,31,32,37,38,40,

41,43,44,46,47

RESERVED

FS Testmode

SRC100#

RESERVED

SSEN

-

FS_A and FS_B

Operation

SRC Frequency

Select

-

Spread Spectrum

Enable

Bit 1

2

Bit 0

1

REF1

REF0

Output Control

Output Control

Type

RW

-

RW

RW

-

RW

RW

RW

0

Disable

-

Normal

100MHz

-

Spread

OFF

Disable

Disable

1

Enable

-

Test Mode

200MHz

-

Spread

ON

Enable

Enable

PWD

0

0

0

0

0

0

1

1

I2C Table: Vendor & Revision ID Register

Byte 7

Pin #

Name

Bit 7

-

RID3

Bit 6

-

RID2

Bit 5

-

RID1

Bit 4

-

RID0

Bit 3

-

VID3

Bit 2

-

VID2

Bit 1

-

VID1

Bit 0

-

VID0

Control Function Type

0

R

-

REVISION ID

R

-

R

-

R

-

R

-

VENDOR ID

R

-

R

-

R

-

1

PWD

-

X

-

X

-

X

-

X

-

0

-

0

-

0

-

1

IDTTM Programmable Timing Control HubTM for Next Gen P4TM Processor

14

0743G—01/26/10

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