Integrated
Circuit
Systems, Inc.
ICS85222
DUAL LVCMOS / LVTTL-TO-
DIFFERENTIAL LVHSTL TRANSLATOR
TABLE 4A. AC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
fMAX
t
PD
tsk(pp)
Output Frequency
Propagation Delay; NOTE 1
Part-to-Part Skew; NOTE 2, 3
ƒ ≤ 350MHz
350
750
950
1150
350
tR
Output Rise Time
20% to 80%
150
800
tF
Output Fall Time
20% to 80%
150
800
IJ 150MHz
48
52
odc
Output Duty Cycle
150 < IJ 250MHz
47
53
250 < IJ 350MHz
45
55
NOTE 1: Measured from VDD/2 of the input to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
Units
MHz
ps
ps
ps
ps
%
%
%
TABLE 4B. AC CHARACTERISTICS, VDD = 2.5V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
fMAX
tPD
tsk(pp)
Output Frequency
Propagation Delay; NOTE 1
Part-to-Part Skew; NOTE 2, 3
ƒ ≤ 350MHz
350
850
1075
1300
450
t
Output Rise Time
20% to 80%
150
800
R
tF
Output Fall Time
20% to 80%
150
800
IJ 150MHz
45
55
odc
Output Duty Cycle
150 < IJ 350MHz
40
60
NOTE 1: Measured from VDD/2 of the input to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
Units
MHz
ps
ps
ps
ps
%
%
85222AM
www.icst.com/products/hiperclocks.html
4
REV. B MARCH 31, 2005