ICS1893AFI(2003) Просмотр технического описания (PDF) - Integrated Circuit Systems
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ICS1893AFI Datasheet PDF : 136 Pages
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ICS1893AF Data Sheet - Release
Table of Contents
Table of Contents
Section
8.14
8.14.1
8.14.2
8.14.3
8.14.4
8.14.5
8.14.6
8.14.7
Chapter 9
9.1
9.2
9.2.1
9.2.2
9.2.3
9.2.4
9.2.5
Title
Page
Register 19: Extended Control Register 2 ............................................................. 95
Node/Repeater Configuration (bit 19.15) ............................................................... 96
Hardware/Software Priority Status (bit 19.14) ........................................................ 96
Remote Fault (bit 19.13) ........................................................................................ 96
ICS Reserved (bits 19.12:8) ................................................................................... 96
Twisted Pair Tri-State Enable, TPTRI (bit 19.7) ..................................................... 96
ICS Reserved (bits 19.6:1) ..................................................................................... 96
Automatic 100Base-TX Power-Down (bit 19.0) ..................................................... 96
Pin Diagram, Listings, and Descriptions ....................................................................... 97
ICS1893AF Pin Diagram ........................................................................................ 97
ICS1893AF Pin Descriptions ................................................................................. 98
Transformer Interface Pins ..................................................................................... 99
Multi-Function (Multiplexed) Pins: PHY Address and LED Pins ...........................100
Configuration Pins.................................................................................................103
MAC Interface Pins ...............................................................................................104
Ground and Power Pins........................................................................................108
Chapter 10
10.1
10.2
10.3
10.4
10.4.1
10.4.2
10.4.3
10.4.4
10.5
10.5.1
10.5.2
10.5.3
10.5.4
10.5.5
10.5.6
10.5.7
10.5.8
10.5.9
10.5.10
10.5.11
10.5.12
10.5.13
DC and AC Operating Conditions............................................................................... 109
Absolute Maximum Ratings .................................................................................109
Recommended Operating Conditions ..................................................................109
Recommended Component Values .....................................................................110
DC Operating Characteristics ..............................................................................111
DC Operating Characteristics for Supply Current ................................................111
DC Operating Characteristics for TTL Inputs and Outputs ..................................111
DC Operating Characteristics for REF_IN ...........................................................112
DC Operating Characteristics for Media Independent Interface ..........................112
Timing Diagrams ..................................................................................................113
Timing for Clock Reference In (REF_IN) Pin .......................................................113
Timing for Transmit Clock (TXCLK) Pins .............................................................114
Timing for Receive Clock (RXCLK) Pins ..............................................................115
100M MII: Synchronous Transmit Timing .............................................................116
10M MII: Synchronous Transmit Timing ..............................................................117
100M/MII Media Independent Interface: Synchronous Receive Timing ...............118
MII Management Interface Timing .......................................................................119
10M Media Independent Interface: Receive Latency ...........................................120
10M Media Independent Interface: Transmit Latency...........................................121
100M/MII Media Independent Interface: Transmit Latency...................................122
100M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission)................123
10M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission)..................124
100M MII Media Independent Interface: Receive Latency....................................125
ICS1893AF, Rev. B 3/07/03
Copyright © 2003, Integrated Circuit Systems, Inc.
All rights reserved.
7
March, 2003
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