HM5117405LTS-6 Просмотр технического описания (PDF) - Hitachi -> Renesas Electronics

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HM5117405LTS-6

16 M EDO DRAM (4-Mword x 4-bit) 4 k Refresh/2 k Refresh

Hitachi -> Renesas Electronics 

HM5116405 Series, HM5117405 Series

To get out of test mode and enter a normal operation mode, perform either a regular -

before- refresh cycle or -only refresh cycle.

20. In a test mode read cycle, the value of tRAC, tAA, tCAC and tCPA is delayed by 2 ns to 5 ns for the

specified value. These parameters should be specified in test mode cycles by adding the above

value to the specified value in this data sheet.

21. tHPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode

read cycles. If both write and read operation are mixed in a EDO page mode

cycle (EDO

page mode mix cycle (1), (2)), minimum value of

than the specified tHPC (min) value. The value of

shown in EDO page mode mix cycle (1) and (2).

cycle (tCAS + tCP + 2 tT) becomes greater

cycle time of mixed EDO page mode is

Data output turns off and becomes high impedance from later risting edge of

and

.

Hold time and turn off time are specified by the timing specifications of later rising edge of

and

between tOHR and tOH, and between tOFR and tOFF.

22. Data output turns off and becomes high impedance from later rising edge of

and

.

Hold time and turn off time are specified by the timing specifications of later rising edge of

and

between tOHR and tOH and between tOFR and tOFF.

23. XXX: H or L (H: VIH (min) VIN VIH (max), L: VIL (min) VIN VIL (max))

///////: Invalid Dout

When the address, clock and input pins are not described on timing waveforms, their pins must

be applied VIH or VIL.

16

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