HI-574A(1997) Просмотр технического описания (PDF) - Intersil
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HI-574A Datasheet PDF : 18 Pages
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HI-574A, HI-674A, HI-774
“Stand-Alone Operation”
Conversion Length
The simplest control interface calls for a singe control line
connected to R/C. Also, CE and 12/8 are wired high, CS and
AO are wired low, and the output data appears in words of
12 bits each.
The R/C signal may have any duty cycle within (and
including) the extremes shown in Figures 8 and 9. In gen-
eral, data may be read when R/C is high unless STS is also
high, indicating a conversion is in progress. Timing parame-
ters particular to this mode of operation are listed below
under “Stand-Alone Mode Timing”.
HI-574A STAND-ALONE MODE TIMING
SYMBOL
PARAMETER
MIN TYP MAX UNITS
tHRL Low R/C Pulse Width
50 -
-
ns
tDS STS Delay from R/C
-
- 200 ns
tHDR Data Valid after R/C Low 25 -
-
ns
tHS STS Delay after Data Valid 300 - 1200 ns
tHRH High R/C Pulse Width 150 -
-
ns
tDDR Data Access Time
-
- 150 ns
Time is measured from 50% level of digital transitions. Tested with a
50pF and 3kΩ load.
A Convert Start transition (see Table 1) latches the state of
AO, which determines whether the conversion continues for
12 bits (AO low) or stops with 8 bits (AO high). If all 12 bits are
read following an 8-bit conversion, the last three LSBs will
read ZERO and DB3 will read ONE. AO is latched because it
is also involved in enabling the output buffers (see “Reading
the Output Data”). No other control inputs are latched.
TABLE 1. TRUTH TABLE FOR HI-X74(A) CONTROL INPUTS
CE CS R/C 12/8 AO
OPERATION
0 X X X X None
X 1 X X X None
↑ 0 0 X 0 Initiate 12-bit conversion
↑ 0 0 X 1 Initiate 8-bit conversion
1 ↓ 0 X 0 Initiate 12-bit conversion
1 ↓ 0 X 1 Initiate 8-bit conversion
1 0 ↓ X 0 Initiate 12-bit conversion
1 0 ↓ X 1 Initiate 8-bit conversion
1 0 1 1 X Enable 12-bit Output
1 0 1 0 0 Enable 8 MSBs Only
HI-674A STAND-ALONE MODE TIMING
1 0 1 0 1 Enable 4 LSBs Plus 4 Trailing
Zeroes
SYMBOL
PARAMETER
MIN TYP MAX UNITS
tHRL Low R/C Pulse Width
50 -
-
ns
tDS STS Delay from R/C
-
- 200 ns
tHDR Data Valid after R/C Low 25 -
-
ns
tHS STS Delay after Data Valid 25 - 850 ns
tHRH High R/C Pulse Width 150 -
-
ns
tDDR Data Access Time
-
- 150 ns
Time is measured from 50% level of digital transitions. Tested with a
50pF and 3kΩ load.
HI-774 STAND-ALONE MODE TIMING
SYMBOL
PARAMETER
MIN TYP MAX UNITS
tHRL Low R/C Pulse Width
50 -
-
ns
tDS STS Delay from R/C
-
- 200 ns
tHDR Data Valid after R/C Low 20 -
-
ns
tHS STS Delay after Data Valid -
- 850 ns
tHRH High R/C Pulse Width 150 -
-
ns
tDDR Data Access Time
-
- 150 ns
Conversion Start
A conversion may be initiated as shown in Table 1 by a logic
transition on any of three inputs: CE, CS or R/C. The last of
the three to reach the correct state starts the conversion, so
one, two or all three may be dynamically controlled. The
nominal delay from each is the same, and if necessary, all
three may change state simultaneously. However, to ensure
that a particular input controls the start of conversion, the
other two should be set up at least 50ns earlier. See the
HI-774 Timing Specifications, Convert Mode.
This variety of HI-X74(A) control modes allows a simple
interface in most system applications. The Convert Start
timing relationships are illustrated in Figure 4.
The output signal STS indicates status of the converter by
going high only while a conversion is in progress. While STS
is high, the output buffers remain in a high impedance state
and data cannot be read. Also, an additional Start Convert
will not reset the converter or reinitiate a conversion while
STS is high.
Reading the Output Data
The output data buffers remain in a high impedance state
until four conditions are met: R/C high, STS low, CE high and
CS low. At that time, data lines become active according to
the state of inputs 12/8 and AO. Timing constraints are
illustrated in Figure 5.
6-965
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