H8S2603 Просмотр технического описания (PDF) - Renesas Electronics

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H8S2603

16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Renesas Electronics 

2.7.8 Memory Indirect@@aa:8 ................................................................................... 41

2.7.9 Effective Address Calculation ................................................................................ 42

2.8 Processing States.................................................................................................................. 45

2.9 Usage Note........................................................................................................................... 46

2.9.1 Notes on Using the Bit Operation Instruction......................................................... 46

Section 3 MCU Operating Modes ....................................................................... 47

3.1 Operating Mode Selection ................................................................................................... 47

3.2 Register Descriptions........................................................................................................... 47

3.2.1 Mode Control Register (MDCR) ............................................................................ 48

3.2.2 System Control Register (SYSCR)......................................................................... 49

3.3 Pin Functions in Each Operating Mode ............................................................................... 50

3.4 Address Map ........................................................................................................................ 51

Section 4 Exception Handling ............................................................................. 53

4.1 Exception Handling Types and Priority............................................................................... 53

4.2 Exception Sources and Exception Vector Table .................................................................. 53

4.3 Reset .................................................................................................................................... 55

4.3.1 Reset Exception Handling ...................................................................................... 55

4.3.2 Interrupts after Reset............................................................................................... 57

4.3.3 State of On-Chip Peripheral Modules after Reset Release ..................................... 58

4.4 Traces................................................................................................................................... 58

4.5 Interrupts.............................................................................................................................. 59

4.6 Trap Instruction.................................................................................................................... 60

4.7 Stack Status after Exception Handling................................................................................. 61

4.8 Usage Note........................................................................................................................... 62

Section 5 Interrupt Controller.............................................................................. 63

5.1 Features................................................................................................................................ 63

5.2 Input/Output Pins................................................................................................................. 65

5.3 Register Descriptions........................................................................................................... 65

5.3.1 Interrupt Priority Registers A to M (IPRA to IPRM) ............................................. 66

5.3.2 IRQ Enable Register (IER) ..................................................................................... 67

5.3.3 IRQ Sense Control Registers H and L (ISCRH, ISCRL)........................................ 68

5.3.4 IRQ Status Register (ISR)....................................................................................... 70

5.4 Interrupt Sources.................................................................................................................. 71

5.4.1 External Interrupts .................................................................................................. 71

5.4.2 Internal Interrupts ................................................................................................... 72

5.5 Interrupt Exception Handling Vector Table......................................................................... 72

5.6 Interrupt Control Modes and Interrupt Operation ................................................................ 76

Rev. 1.00 Jan. 24, 2008 Page x of xxxvi

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