N74F85D Просмотр технического описания (PDF) - Philips Electronics
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N74F85D Datasheet PDF : 10 Pages
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Philips Semiconductors
4-bit magnitude comparator
Product specification
74F85
FEATURES
• High-impedance NPN base inputs for reduced loading
(20µA in High and Low states)
• Magnitude comparison of any binary words
• Serial or parallel expansion without extra gating
DESCRIPTION
The 74F85 is a 4-bit magnitude comparator that can be expanded to
almost any length. It compares two 4-bit binary, BCD, or other
monotonic codes and presents the three possible magnitude results
at the outputs. The 4-bit inputs are weighted (A0–A3) and (B0–B3)
where A3 and B3 are the most significant bits. The operation of the
74F85 is described in the Function Table, showing all possible logic
conditions. The upper part of the table describes the normal
operation under all conditions that will occur in a single device or in
a series expansion scheme. In the upper part of the table the three
outputs are mutually exclusive. In the lower part of the table, the
outputs reflect the feed-forward conditions that exist in the parallel
expansion scheme. The expansion inputs IA>B, and IA=B and IA<B
are the least significant bit positions. When used for series
expansion, the A>B, A=B and A<B outputs of the lease significant
word are connected to the corresponding IA>B, IA=B and IA<B inputs
of the next higher stage. Stages can be added in this manner to any
length, but a propagation delay penalty of about 15ns is added with
each additional stage. For proper operation, the expansion inputs of
the least significant word should be tied as follows: IA>B = Low,
IA=B = High, and IA<B = Low.
PIN CONFIGURATION
B3 1
IA<B 2
IA=B 3
IA>B 4
A>B 5
A=B 6
A<B 7
GND 8
16 VCC
15 A3
14 B2
13 A2
12 A1
11 B1
10 A0
9 B0
SF00075
TYPE
74F85
TYPICAL
PROPAGATION
DELAY
7.0ns
TYPICAL
SUPPLY CURRENT
(TOTAL)
40mA
ORDERING INFORMATION
DESCRIPTION
16-pin plastic DIP
COMMERCIAL RANGE
VCC = 5V ±10%,
Tamb = 0°C to +70°C
N74F85N
16-pin plastic SO
N74F85D
PKG DWG #
SOT38-4
SOT162-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
74F (U.L.) HIGH/LOW
A0–A3
Comparing inputs
1.0/0.033
B0–B3
Comparing inputs
1.0/0.033
IA<B, IA=B, IA>B
Expansion inputs (active High)
1.0/0.033
A<B, A=B, A>B
Data outputs (active High)
50/33
NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
LOAD VALUE HIGH/LOW
20µA/20µA
20µA/20µA
20µA/20µA
1.0mA/20mA
LOGIC SYMBOL
IEC/IEEE SYMBOL
10 12 13 15
9 11 14 1
A0 A1 A2 A3
B0 B1 B2 B3
2
IA<B
3
IA=B
4
IA>B
A>B A=B A<B
VCC = Pin 16
GND = Pin 8
5
6
7
SF00076
10
COMP
0
12
13
P
15
3
9
0
P<Q
7
11
6
P=Q
14
Q
5
P>Q
1
3
2
<
3
=
4
>
SF00077
September 27, 1994
2
853–0055 13903
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