FM93C56 Просмотр технического описания (PDF) - Fairchild Semiconductor
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Компоненты Описание
производитель
FM93C56
Fairchild Semiconductor
FM93C56 Datasheet PDF : 16 Pages
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Timing Diagrams (Continued)
PROTECT REGISTER CLEAR CYCLE (PRCLEAR)
;;;;;;;;;
PRE
;;;;;;;;;
PE
;;;;;;;;;
tCS
CS
SK
1 1 1 A7 A6
A1 A0
DI
Start Opcode
Bit Bits(2) High - Z
DO
93CS56:
Address bits pattern -> 1-1-1-1-1-1-1-1
Address
Bits(8)
tWP
Ready
Busy
PROTECT REGISTER WRITE CYCLE (PRWRITE)
;;;;;;;;;
PRE
;;;;;;;;;
PE
;;;;;;;;;
tCS
CS
SK
1 0 1 A7 A6
A1 A0
DI
tWP
Start Opcode
Address
Bit Bits(2) High - Z Bits(8)
DO
Ready
Busy
93CS56:
Address bits pattern -> x-A6-A5-A4-A3-A2-A1-A0; (x -> Don't Care, can be 0 or 1); ( A6-A0 -> User defined )
PROTECT REGISTER DISABLE CYCLE (PRDS)
;;;;;;;;;
PRE
;;;;;;;;;
PE
;;;;;;;;;
tCS
CS
SK
1 0 0 A7 A6
A1 A0
DI
Start Opcode
Address
Bit
Bits(2) High - Z Bits(8)
DO
93CS56:
Address bits pattern -> 0-0-0-0-0-0-0-0
tWP
Ready
Busy
FM93CS56 Rev. C.1
12
www.fairchildsemi.com
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