FM93CS46TLV Просмотр технического описания (PDF) - Fairchild Semiconductor
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FM93CS46TLV Datasheet PDF : 13 Pages
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Timing Diagrams (Continued)
ERASE CYCLE (ERASE)
tCS
CS
SK
1 1 1 A5 A4
A1 A0
DI
Start Opcode
Address
Bit
Bits(2) High - Z Bits(6)
DO
93C46:
Address bits pattern -> User defined
tWP
Ready
Busy
ERASE ALL CYCLE (ERAL)
tCS
CS
SK
1 0 0 A5 A4
A1 A0
DI
tWP
Start Opcode
Address
Bit
Bits(2) High - Z Bits(6)
DO
Busy
93C46:
Address bits pattern -> 1-0-x-x-x-x; (x -> Don’t Care, can be 0 or 1)
Ready
CLEARING READY STATUS
CS
SK
DI
High - Z
DO
Busy
Ready
Start
Bit
High - Z
Note: This Start bit can also be part of a next instruction. Hence the cycle
can be continued (instead of getting terminated, as shown) as if a new
instruction is being issued.
FM93C46 Rev. D.1
10
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