M5M410092BFP Просмотр технического описания (PDF) - MITSUBISHI ELECTRIC

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M5M410092BFP

Overview of 3D-RAM and Its Functional Blocks

MITSUBISHI ELECTRIC  

MITSUBISHI

ELECTRONIC DEVICE GROUP

Rev. 1.03

3D-RAM (M5M410092B)

Pixel Buffer

The Pixel Buffer is a 2048-bit SRAM organized

into eight 256-bit blocks, as seen in Figure 1.3,

and functions as a level-one write-back pixel

cache. It has a 256-bit read/write port, a 32-bit

read port, and a 32-bit write port. Referring to

Figure 1.6, the 256-bit read/write port is

connected to the Global Bus via a Write Buffer,

and the two 32-bit ports are connected to the Pixel

ALU and the pixel data pins. All three ports can be

used simultaneously as long as the same memory

cell is not accessed. If the two 32-bit ports access

the same cell, the write operation will be

successful but the read data will be undefined.

A 1-bit Dirty Tag bit is assigned to each byte data

in the Pixel Buffer. Therefore, each block in the

Pixel Buffer is associated with a 32-bit Dirty Tag in

the dual-port Dirty Tag RAM. When a block is

transferred from the sense amplifiers to the Pixel

Buffer through the 256-bit port, the corresponding

32-bit Dirty Tag is cleared. When a block is

transferred from the Pixel Buffer to a DRAM bank,

the Dirty Tag determines which bytes are actually

written. This feature can save as much as 50% of

the power consumed by a 256-bit block write

operation without the Dirty Tag.

The cache set associativity is determined external

to the 3D-RAM, thereby permitting optimal cache

design tailored to the particular graphics system.

Video Buffers

Each video buffer receives 640-bit data at a time

from one of the two DRAM banks connected to it.

(The reader is reminded of the 3D-RAM block

diagram in Figure 1.2.) sixteen bits of data are

shifted out onto the video data pins every video

clock cycle at 14-ns rate. It takes 40 video clocks

to shift all data out of a video buffer. The video

counter counts modulo 40 and toggles the buffer

select line when the count wraps around to 0.

These two video buffers can be alternated to

provide a seamless stream of video data.

A DRAM Page

80 bytes

0

1

2

14

15

640

Video Buffer (40 x 16 bits)

8 7 6 5 4 3 2 1 0 DRAM_A[8..0]

Selecting one of the

sixteen 80-byte scan

lines from the page

Ignored

16

Video Data Out

Other functions

Figure 1.5 Video transfer from a DRAM page to the Video Buffer

7

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