DSP56366P Просмотр технического описания (PDF) - Freescale Semiconductor

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DSP56366P

24-Bit Audio Digital Signal Processor

Freescale Semiconductor 

sure that the part has completed its HI port programming (e.g., by setting the INIT bit in ICR then

polling it and waiting it to be cleared, then reading the ISR or by writing the TREQ/RREQ together

with the INIT and then polling INIT, ISR, and the HOREQ pin).

5.5.2 DSP Programming Considerations

• Synchronization of Status Bits from Host to DSP—DMA, HF1, HF0, HCP, HTDE, and HRDF

status bits are set or cleared by the host processor side of the interface. These bits are individually

synchronized to the DSP clock. (Refer to the user’s manual for descriptions of these status bits.)

• Reading HF0 and HF1 as an Encoded Pair—Care must be exercised when reading status bits

HF0 and HF1 as an encoded pair, (i.e., the four combinations 00, 01, 10, and 11 each have

significance). A very small probability exists that the DSP will read the status bits synchronized

during transition. Therefore, HF0 and HF1 should be read twice and checked for consensus.

DSP56366 Technical Data, Rev. 3.1

5-6

Freescale Semiconductor

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