External Memory Expansion Port (Port A)
3.10 External Memory Expansion Port (Port A)
3.10.1
SRAM Timing
Table 3-8 SRAM Read and Write Accesses 100 and 120 MHz1
No.
Characteristics
100 Address valid and AA assertion pulse width3
101 Address and AA valid to WR assertion
102 WR assertion pulse width
103 WR deassertion to address not valid
Symbol
tRC, tWC
tAS
tWP
tWR
Expression2
100 MHz
120 MHz
Unit
Min Max Min Max
(WS + 1) × TC − 4.0 16.0 — 12.0 — ns
[1 ≤ WS ≤ 3]
(WS + 2) × TC − 4.0 56.0 — 46.0 — ns
[4 ≤ WS ≤ 7]
(WS + 3) × TC − 4.0 106.0 — 87.0 — ns
[WS ≥ 8]
100 MHz:
0.25 × TC − 2.0
[WS = 1]
0.5 — 0.1 — ns
1.25 × TC − 2.0
[WS ≥ 4]
10.5 — 8.4 — ns
100 MHz:
1.5 × TC − 4.0
[WS = 1]
11.0 — 8.5 — ns
All frequencies:
WS × TC − 4.0
[2 ≤ WS ≤ 3]
16.0 — 12.7 — ns
(WS − 0.5) × TC − 4.0 31.0 --- 25.2 —
[WS ≥ 4]
100 MHz:
0.25 × TC − 2.0
[1 ≤ WS ≤ 3]
0.5 — 0.1 — ns
1.25 × TC − 2.0
[4 ≤ WS ≤ 7]
10.5 — 8.4 —
2.25 × TC − 2.0
[WS ≥ 8]
20.5 — 16.7 —
All frequencies:
1.25 × TC − 4.0
[4 ≤ WS ≤ 7]
8.5 — 6.4 —
2.25 × TC − 4.0
[WS ≥ 8]
18.5 — 14.7 —
DSP56362 Technical Data, Rev. 4
3-14
Freescale Semiconductor