DSP56366 Просмотр технического описания (PDF) - Motorola => Freescale

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производитель

DSP56366

Digital Signal Processor

Motorola => Freescale 

ED7

ED15

Freescale Semiconductor, Inc.

Chip Errata

DSP56366 Digital Signal Processor

Mask:2J26D

Errata Description

Description (added 1/27/98):

Applies

to Mask

2J26D

When activity passes from one DMA channel to another and the DMA

interface accesses external memory (which requires one or more wait

states), the DACT and DCH status bits in the DMA Status Register

(DSTR) may indicate improper activity status for DMA Channel 0

(DACT = 1 and DCH[2:0] = 000).

Workaround:

None.

Description (added 7/21/98):

2J26D

The DRAM Control Register (DCR) should not be changed while refresh

is enabled. If refresh is enabled only a write operation that disables refresh

is allowed.

Workaround:

First disable refresh by clearing the BREN bit, than change other bits in the

DCR register, and finally enable refresh by setting the BREN bit.

DSP56366 Errata

 1997 -2001, Motorola

For Mor3e66ICnfEo2rJm26aDt_io0n_0On This Product,

Go to: www.freescale.com

NG 11/12/01 pg. 14 of 25

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