CY7C4255V Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C4255V Datasheet PDF : 20 Pages
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CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
Architecture
The CY7C4255/65/75/85V consists of an array of
8K/16K/32K/64K words of 18 bits each (implemented by a
dual-port array of SRAM cells), a read pointer, a write pointer,
control signals (RCLK, WCLK, REN, WEN, RS), and flags (EF,
PAE, HF, PAF, FF). The CY7C4255/65/75/85V also includes
the control signals WXI, RXI, WXO, RXO for depth expansion.
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Reset (RS)
cycle. This causes the FIFO to enter the Empty condition sig-
nified by EF being LOW. All data outputs go LOW after the
falling edge of RS only if OE is asserted. In order for the FIFO
to reset to its default state, the user must not read or write while
RS is LOW.
normal read/write operation. When the LD pin is set LOW, and
WEN is LOW, the next offset register in sequence is written.
The contents of the offset registers can be read on the output
lines when the LD pin is set LOW and REN is set LOW; then,
data can be read on the LOW-to-HIGH transition of the read
clock (RCLK).
Table 1. Write Offset Register
LD WEN WCLK[35]
Selection
00
Writing to offset registers:
Empty Offset
Full Offset
01
No Operation
FIFO Operation
10
Write Into FIFO
When the WEN signal is active (LOW), data present on the
D0–17 pins is written into the FIFO on each rising edge of the
WCLK signal. Similarly, when the REN signal is active LOW,
data in the FIFO memory will be presented on the Q0–17 out-
puts. New data will be presented on each rising edge of RCLK
while REN is active LOW and OE is LOW. REN must set up
tENS before RCLK for it to be a valid read function. WEN must
occur tENS before WCLK for it to be a valid write function.
An output enable (OE) pin is provided to three-state the Q0–17
outputs when OE is deasserted. When OE is enabled (LOW),
data in the output register will be available to the Q0–17 outputs
after tOE. If devices are cascaded, the OE function will only
output data on the FIFO that is read enabled.
The FIFO contains overflow circuitry to disallow additional
writes when the FIFO is full, and under flow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO
maintains the data of the last valid read on its Q0–17 outputs
even after additional reads occur.
11
No Operation
Flag Operation
The CY7C4255/65/75/85V devices provide five flag pins to in-
dicate the condition of the FIFO contents. Empty and Full are
synchronous. PAE and PAF are synchronous if VCC/SMODE
is tied to VSS.
Full Flag
The Full Flag (FF) will go LOW when device is Full. Write op-
erations are inhibited whenever FF is LOW regardless of the
state of WEN. FF is synchronized to WCLK, i.e., it is exclusive-
ly updated by each rising edge of WCLK.
Empty Flag
Programming
The Empty Flag (EF) will go LOW when the device is empty.
Read operations are inhibited whenever EF is LOW, regard-
The CY7C4255/65/75/85V devices contain two 16-bit offset
registers. Data present on D0–15 during a program write will
determine the distance from Empty (Full) that the Almost Emp-
ty (Almost Full) flags become active. If the user elects not to
program the FIFO’s flags, the default offset values are used
(see Table 2). When the Load LD pin is set LOW and WEN is
set LOW, data on the inputs D0–15 is written into the Empty
offset register on the first LOW-to-HIGH transition of the write
clock (WCLK). When the LD pin and WEN are held LOW then
data is written into the Full offset register on the second LOW-
to-HIGH transition of the write clock (WCLK). The third transi-
tion of the write clock (WCLK) again writes to the Empty offset
less of the state of REN. EF is synchronized to RCLK, i.e., it is
exclusively updated by each rising edge of RCLK.
Programmable Almost Empty/Almost Full Flag
The CY7C4255/65/75/85V features programmable Almost
Empty and Almost Full Flags. Each flag can be programmed
(described in the Programming section) a specific distance
from the corresponding boundary flags (Empty or Full). When
the FIFO contains the number of words or fewer for which the
flags have been programmed, the PAF or PAE will be assert-
ed, signifying that the FIFO is either Almost Full or Almost
Empty. See Table 2 for a description of programmable flags.
register (see Table 1). Writing all offset registers does not have When the SMODE pin is tied LOW, the PAF flag signal transi-
to occur at one time. One or two offset registers can be written tion is caused by the rising edge of the write clock and the PAE
and then, by bringing the LD pin HIGH, the FIFO is returned to flag transition is caused by the rising edge of the read clock.
Note:
35. The same selection sequence applies to reading from the registers. REN is enabled and read is performed on the LOW-to-HIGH transition of RCLK.
Document #: 38-06012 Rev. *A
Page 15 of 20
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