CY7C1345F-133AC Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C1345F-133AC Datasheet PDF : 17 Pages
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CY7C1345F
Maximum Ratings
Current into Outputs (LOW)......................................... 20 mA
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... >200 mA
Operating Range
Ambient
Range Temperature]
VDD
VDDQ
DC Voltage Applied to Outputs
in three-state ....................................... –0.5V to VDDQ + 0.5V
DC Input Voltage....................................–0.5V to VDD + 0.5V
Commercial 0°C to +70°C 3.3V −5%/+10% 2.5V –5%
Industrial –40°C to +85°C
to VDD
Electrical Characteristics Over the Operating Range [8, 9]
CY7C1345F
Parameter
Description
Test Conditions
Min. Max. Unit
VDD
VDDQ
VOH
VOL
VIH
VIL
IX
Power Supply Voltage
I/O Supply Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage[8]
Input Load Current
(except ZZ and MODE)
VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA
VDDQ = 2.5V, VDD = Min., IOH = –1.0 mA
VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA
VDDQ = 2.5V, VDD = Min., IOL = 1.0 mA
VDDQ = 3.3V
VDDQ = 2.5V
VDDQ = 3.3V
VDDQ = 2.5V
GND ≤ VI ≤ VDDQ
3.135 3.6
V
2.375 VDD
V
2.4
V
2.0
V
0.4
V
0.4
V
2.0 VDD + 0.3V V
1.7 VDD + 0.3V V
–0.3 0.8
V
–0.3 0.7
V
−5
5
µA
Input Current of MODE
Input = VSS
–30
µA
Input = VDD
5
µA
Input Current of ZZ
Input = VSS
–5
µA
Input = VDD
30
µA
IOZ
Output Leakage Current
GND ≤ VI ≤ VDD, Output Disabled
–5
5
µA
IOS
Output Short Circuit Current
VDD = Max., VOUT = GND
–300 µA
IDD
VDD Operating Supply Current VDD = Max., IOUT = 0 mA,
7.5-ns cycle, 133 MHz
f = fMAX= 1/tCYC
8.0-ns cycle, 117 MHz
225 mA
220 mA
10-ns cycle, 100 MHz
205 mA
15-ns cycle, 66 MHz
195 mA
ISB1
Automatic CE Power-down
Max. VDD, Device Deselected, 7.5-ns cycle, 133 MHz
Current—TTL Inputs
VIN ≥ VIH or VIN ≤ VIL, f = fMAX,
inputs switching
8.0-ns cycle, 117 MHz
10-ns cycle, 100 MHz
90 mA
85 mA
80 mA
15-ns cycle, 66 MHz
60 mA
ISB2
Automatic CE Power-down
Max. VDD, Device Deselected, All speeds
Current—CMOS Inputs
VIN ≥ VDD – 0.3V or VIN ≤ 0.3V,
f = 0, inputs static
40 mA
Shaded areas contain advance information.
Notes:
8. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > -2V (Pulse width less than tCYC/2).
9. TPower-up: Assumes a linear ramp from 0v to VDD(min.) within 200ms. During this time VIH < VDD and VDDQ < VDD.
Document #: 38-05214 Rev. *C
Page 8 of 17
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