CY7C1345F-133AC Просмотр технического описания (PDF) - Cypress Semiconductor

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Компоненты Описание

производитель

CY7C1345F-133AC

4-Mb (128K x 36) Flow-Through Sync SRAM

Cypress Semiconductor 

CY7C1345F

Pin Descriptions (continued)

Name

OE

ADV

ADSP

ADSC

ZZ

DQs

DQPA,

DQPB

DQPC,

DQPD

VDD

VSS

VDDQ

VSSQ

MODE

NC

TQFP

86

83

84

85

64

52,53,56,

57,58,59,

62,63,68,

69,72,73,

74,75,78,

79,2,3,6,

7,8,9,12,

13,18,19,

22,23,24,

25,28,29,

51,80,1,30

15,41,

65, 91

17,40,

67,90

4,11,20,

27,54,61,

70,77

5,10,21,

26,55,60,

71,76

31

14,16,38,

39,42,43,

66,

BGA

I/O

Description

F4

Input- Output Enable, asynchronous input, active LOW. Controls the

Asynchronous direction of the I/O pins. When LOW, the I/O pins behave as outputs.

When deasserted HIGH, I/O pins are three-stated, and act as input

data pins. OE is masked during the first clock of a read cycle when

emerging from a deselected state.

G4

Input- Advance Input signal, sampled on the rising edge of CLK. When

Synchronous asserted, it automatically increments the address in a burst cycle.

A4

Input- Address Strobe from Processor, sampled on the rising edge of

Synchronous CLK, active LOW. When asserted LOW, addresses presented to the

device are captured in the address registers. A[1:0] are also loaded

into the burst counter. When ADSP and ADSC are both asserted,

only ADSP is recognized. ASDP is ignored when CE1 is deasserted

HIGH

B4

Input- Address Strobe from Controller, sampled on the rising edge of

Synchronous CLK, active LOW. When asserted LOW, addresses presented to the

device are captured in the address registers. A[1:0] are also loaded

into the burst counter. When ADSP and ADSC are both asserted,

only ADSP is recognized.

T7

Input- ZZ “sleep” Input, active HIGH. When asserted HIGH places the

Asynchronous device in a non-time-critical “sleep” condition with data integrity

preserved. For normal operation, this pin has to be LOW or left

floating. ZZ pin has an internal pull-down.

K6,K7,L6,

L7,M6,N6,

N7,P7,D7,

E6,E7,F6,

G6,G7,H6,

H7,D1,E1,

E2,F2,G1,

G2,H1,H2,

K1,K2,L1,

L2,M2,N1

N2,P1,P6,D6,

D2,P2

I/O-

Bidirectional Data I/O lines. As inputs, they feed into an on-chip

Synchronous data register that is triggered by the rising edge of CLK. As outputs,

they deliver the data contained in the memory location specified by

the addresses presented during the previous clock rise of the read

cycle. The direction of the pins is controlled by OE. When OE is

asserted LOW, the pins behave as outputs. When HIGH, DQs and

DQP[A:D] are placed in a three-state condition.

C4,J2,J4, Power Supply Power supply inputs to the core of the device.

R4,J6

D3,D5,E3,E5,

F3,F5,H3,H5,

K3,K5,M3,M5,

N3,N5,P3,P5

Ground

Ground for the core of the device.

A1,A7,F1,F7,

J1,J7,M1,M7,

U1,U7

I/O Power Power supply for the I/O circuitry.

Supply

–

I/O Ground Ground for the I/O circuitry.

R3

B1,B7,C1,C7,

D4,J3,J5,L4,

R1,R5,R7,T1,

T2,T6,U2,U3,

U4,U5,U6

Input-

Static

Selects Burst Order. When tied to GND selects linear burst

sequence. When tied to VDD or left floating selects interleaved burst

sequence. This is a strap pin and should remain static during device

operation. Mode Pin has an internal pull-up.

No Connects. Not Internally connected to the die.

Document #: 38-05214 Rev. *C

Page 4 of 17

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