CY7C1327G(2006) Просмотр технического описания (PDF) - Cypress Semiconductor

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производитель

CY7C1327G
(Rev.:2006)

4-Mbit (256K x 18) Pipelined Sync SRAM

Cypress Semiconductor 

Switching Waveforms

Read Cycle Timing[16]

tCYC

CY7C1327G

CLK

ADSP

ADSC

ADDRESS

GW, BWE,

BW[A:B]

CE

ADV

OE

Data Out (Q)

tCH tCL

t

ADS

tADH

tADS tADH

tAS tAH

A1

A2

tWES tWEH

A3

Burst continued with

new base address

tCES tCEH

Deselect

cycle

tADVS tADVH

tCLZ

High-Z

tCO

tOEHZ

Q(A1)

Single READ

ADV

suspends

burst.

tOEV

tCO

tOELZ

tDOH

Q(A2) Q(A2 + 1)

Q(A2 + 2)

Q(A2 + 3)

BURST READ

tCHZ

Q(A2) Q(A2 + 1)

Burst wraps around

to its initial state

DON’T CARE UNDEFINED

Note:

16. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

Document #: 38-05519 Rev. *F

Page 11 of 18

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