CY7C1297H-133AXC Просмотр технического описания (PDF) - Cypress Semiconductor

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производитель

CY7C1297H-133AXC

1-Mbit (64K x 18) Flow-Through Sync SRAM

Cypress Semiconductor 

Timing Diagrams (continued)

Write Cycle Timing[16, 17]

CY7C1297H

tCYC

CLK

ADSP

ADSC

ADDRESS

BWE,

BW[A:B]

GW

CE

ADV

t

CH

t

CL

tADS tADH

tADS tADH

tAS tAH

A1

A2

Byte write signals are ignored for first cycle when

ADSP initiates burst.

tCES tCEH

tt

WES WEH

ADSC extends burst.

tADS tADH

A3

tWES tWEH

tADVS tADVH

ADV suspends burst.

OE

tDS t DH

Data in (D)

Data Out (Q)

High-Z

D(A1)

tOEHZ

BURST READ

Single WRITE

D(A2)

D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3)

BURST WRITE

DON’T CARE UNDEFINED

Note:

17. Full width Write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A:B] LOW.

D(A3)

D(A3 + 1) D(A3 + 2)

Extended BURST WRITE

Document #: 38-05669 Rev. *B

Page 11 of 15

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