CY7B992-7LMB(2001) Просмотр технического описания (PDF) - Cypress Semiconductor

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Компоненты Описание

производитель

CY7B992-7LMB
(Rev.:2001)

Programmable Skew Clock Buffer

Cypress Semiconductor 

CY7B991

CY7B992

20–MHz

DISTRIBUTION

CLOCK

FB

REF

FS

4F0

4F1

3F0

3F1

2F0

2F1

1F0

1F1

TEST

REF

4Q0

4Q1

3Q0

3Q1

2Q0

2Q1

1Q0

1Q1

Z0

80-MHz

INVERTED

20-MHz

Z0

80-MHz

ZERO SKEW

Z0

LOAD

LOAD

LOAD

80-MHz

SKEWED –3.125 ns (–4tU) Z0

LOAD

7B991–14

Figure 7. Multi-Function Clock Driver

SYSTEM

CLOCK

REF

FB

REF

FS

4F0

4Q0

4F1

4Q1

3F0

3Q0

3F1

3Q1

2F0

2Q0

2F1

2Q1

1F0

1Q0

1F1

1Q1

TEST

L1

L2

LOAD

Z0

LOAD

Z0

L3

L4

Z0

Z0

FB

REF

FS

4F0

4F1

4Q0

4Q1

3F0 3Q0

3F1 3Q1

2F0 2Q0

2F1 2Q1

1F0 1Q0

1F1 1Q1

TEST

LOAD

LOAD

LOAD

Figure 8. Board-to-Board Clock Distribution

7B991–15

Figure 8 shows the CY7B991/992 connected in series to con-

struct a zero-skew clock distribution tree between boards. De-

lays of the downstream clock buffers can be programmed to

compensate for the wire length (i.e., select negative skew

equal to the wire delay) necessary to connect them to the mas-

ter clock source, approximating a zero-delay clock tree. Cas-

caded clock buffers will accumulate low-frequency jitter be-

cause of the non-ideal filtering characteristics of the PLL filter.

It is recommended that not more than two clock buffers be

connected in series.

Document #: 38-07138 Rev. **

Page 12 of 15

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