CY223811SI-CKN Просмотр технического описания (PDF) - Cypress Semiconductor
Номер в каталоге
Компоненты Описание
производитель
CY223811SI-CKN Datasheet PDF : 11 Pages
| |||
CY22381
CY223811
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Supply voltage ..............................................–0.5 V to +7.0 V
DC input voltage .............................–0.5 V to + (VDD + 0.5 V)
Storage temperature..................................... –65 °C +125 °C
Junction temperature.................................................. 125 °C
Data retention at Tj = 125 °C.................................> 10 years
Maximumrprogamming cycles..........................................100
Package power dissipation....................................... 250 mW
Static discharge voltage
(per MIL-STD-883, Method 3015) ........................... 2000V
Latch up (per JEDEC 17) .................................... ±200 mA
Operating Conditions
Parameter
Description
Min
Typ
VDD
Supply voltage
TA
Commercial operating temperature, ambient
Industrial operating temperature, ambient
3.135
3.3
0
–
–40
–
CLOAD_OUT
fREF
Max. load capacitance
External reference crystal
External reference clock[2], cCommercial
–
–
8
–
1
–
External reference clock[2], industrial
1
–
tPU
Power up time for all VDD's to reach minimum specified voltage (power 0.05
–
ramps must be monotonic)
Max
3.465
+70
+85
15
30
166
150
500
Unit
V
°C
°C
pF
MHz
MHz
MHz
ms
Recommended Crystal Specifications
Parameter
Description
Description
Min
FNOM
Nominal crystal frequency Parallel resonance, fundamental mode
8
CLNOM
Nominal load capacitance
8
R1
Equivalent series resistance Fundamental mode
–
(ESR)
DL
Crystal drive level
No external series resistor assumed
–
Typ.
–
–
–
0.5
Max
Unit
30
MHz
20
pF
50
2
mW
Electrical Characteristics
Parameter
Description
IOH
Output high current[3]
IOL
Output low current[3]
CXTAL_MIN Crystal load capacitance[3]
CXTAL_MAX Crystal load capacitance[3]
CIN
Input pin capacitance[3]
VIH
HIGH-level input voltage
VIL
LOW-level input voltage
IIH
Input HIGH current
IIL
Input LOW current
IOZ
Output leakage current
Conditions[1]
VOH = VDD – 0.5, VDD = 3.3 V
VOL = 0.5 V, VDD = 3.3 V
Capload at minimum setting
Capload at maximum setting
Except crystal pins
CMOS levels,% of VDD
CMOS levels,% of VDD
VIN = VDD – 0.3 V
VIN = +0.3 V
Three-state outputs
Min
Typ
12
24
12
24
–
6
–
30
–
7
70%
–
–
–
–
<1
–
<1
–
–
Max
–
–
–
–
–
–
30%
10
10
10
Unit
mA
mA
pF
pF
pF
VDD
VDD
A
A
A
Notes
1. Unless otherwise noted, Electrical and Switching Characteristics are guaranteed across these operating conditions.
2. External input reference clock must have a duty cycle between 40% and 60%, measured at VDD/2.
3. Guaranteed by design, not 100% tested.
Document #: 38-07012 Rev. *I
Page 5 of 11
[+] Feedback
Share Link: 