CY14B256KA(2009) Просмотр технического описания (PDF) - Cypress Semiconductor

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CY14B256KA
(Rev.:2009)

256 Kbit (32K x 8) nvSRAM with Real Time Clock

Cypress Semiconductor 

CY14B256KA

Table 4. Register Map Detail (continued)

Register

CY14B256KA

0x7FF4

M

0x7FF3

M

0x7FF2

M

0x7FF1

0x7FF0

WDF

AF

PF

OSCF

CAL

W

R

Description

Alarm - Hours

D7

D6

D5

D4

D3

D2

D1

D0

M

0

10s Alarm Hours

Alarm Hours

Contains the alarm value for the hours and the mask bit to select or deselect the hours value.

Match. When this bit is set to 0, the hours value is used in the alarm match. Setting this bit to 1 causes the

match circuit to ignore the hours value.

Alarm - Minutes

D7

D6

D5

D4

D3

D2

D1

D0

M

10s Alarm Minutes

Alarm Minutes

Contains the alarm value for the minutes and the mask bit to select or deselect the minutes value.

Match. When this bit is set to 0, the minutes value is used in the alarm match. Setting this bit to 1 causes the

match circuit to ignore the minutes value.

Alarm - Seconds

D7

D6

D5

D4

D3

D2

D1

D0

M

10s Alarm Seconds

Alarm Seconds

Contains the alarm value for the seconds and the mask bit to select or deselect the seconds’ value.

Match. When this bit is set to 0, the seconds value is used in the alarm match. Setting this bit to 1 causes the

match circuit to ignore the seconds value.

Time Keeping - Centuries

D7

D6

D5

D4

D3

D2

D1

D0

10s Centuries

Centuries

Contains the BCD value of centuries. Lower nibble (four bits) contains the lower digit and operates from 0 to 9;

upper nibble (two bits) contains the upper digit and operates from 0 to 9. The range for the register is 0-99

centuries.

Flags

D7

D6

D5

D4

D3

D2

D1

D0

WDF

AF

PF

OSCF

0

CAL

W

R

Watchdog Timer Flag. This read only bit is set to 1 when the watchdog timer is allowed to reach 0 without being

reset by the user. It is cleared to 0 when the Flags register is read or on power up

Alarm Flag. This read only bit is set to 1 when the time and date match the values stored in the alarm registers

with the match bits = 0. It is cleared when the Flags register is read or on power up.

Power Fail Flag. This read only bit is set to 1 when power falls below the power fail threshold VSWITCH. It is

cleared to 0 when the Flags register is read or on power up.

Oscillator Fail Flag. Set to 1 on power up if the oscillator is enabled and not running in the first 5 ms of operation.

This indicates that RTC backup power failed and clock value is no longer valid. This bit survives power cycle

and is never cleared internally by the chip. The user must check for this condition and write '0' to clear this flag.

Calibration Mode. When set to 1, a 512 Hz square wave is output on the INT pin. When set to 0, the INT pin

resumes normal operation. This bit defaults to 0 (disabled) on power up.

Write Enable: Setting the W bit to 1 freezes updates of the RTC registers. The user can then write to RTC

registers, Alarm registers, Calibration register, Interrupt register and Flags register. Setting the W bit to 0

transfers the contents of the RTC registers to the time keeping counters if the time is changed (a new base time

is loaded). This bit defaults to 0 on power up.

Read Enable: Setting R bit to 1, stops clock updates to user RTC registers so that clock updates are not seen

during the reading process. Set R bit to 0 to resume clock updates to the holding register. Setting this bit does

not require W bit to be set to 1. This bit defaults to 0 on power up.

Document #: 001-55720 Rev. *A

Page 15 of 26

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