CY14B101LA-SZ45XIT Просмотр технического описания (PDF) - Cypress Semiconductor

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производитель

CY14B101LA-SZ45XIT

1 Mbit (128K x 8/64K x 16) nvSRAM

Cypress Semiconductor 

PRELIMINARY

CY14B101LA, CY14B101NA

Address

CE

BHE, BLE

WE

Data Input

Data Output

Figure 9. SRAM Write Cycle #2: CE Controlled [3, 17, 18, 21]

tWC

Address Valid

tSA

tSCE

tHA

tBW

tPWE

tSD

tHD

Input Data Valid

High Impedance

Address

CE

BHE, BLE

WE

Data Input

Data Output

Figure 10. SRAM Write Cycle #3: BHE and BLE Controlled [3, 17, 18, 21]

tWC

Address Valid

tSCE

tSA

tBW

tHA

tAW

tPWE

tSD

tHD

Input Data Valid

High Impedance

Document #: 001-42879 Rev. *C

Page 12 of 24

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