CY14B101LA-ZS45XI(2011) Просмотр технического описания (PDF) - Cypress Semiconductor

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CY14B101LA-ZS45XI
(Rev.:2011)

1-Mbit (128 K × 8/64 K × 16) nvSRAM

Cypress Semiconductor 

CY14B101LA

CY14B101NA

Software Controlled STORE/RECALL Cycle

Parameter[37, 38]

Description

tRC

tSA

tCW

tHA

tRECALL

STORE/RECALL initiation cycle time

Address setup time

Clock pulse width

Address hold time

RECALL duration

Switching Waveforms

20 ns

Min Max

20

–

0

–

15

–

0

–

–

200

25 ns

Min Max

25

–

0

–

20

–

0

–

–

200

45 ns

Unit

Min Max

45

–

ns

0

–

ns

30

–

ns

0

–

ns

–

200

µs

Figure 12. CE and OE Controlled Software STORE/RECALL Cycle[38]

tRC

tRC

Address

Address #1

tSA

tCW

Address #6

tCW

CE

tSA

OE

tHA

tHA

tHA

tHA

HSB (STORE only)

DQ (DATA)

tLZCE

tHZCE

t DELAY

39

Note

High Impedance

tSTORE/tRECALL

tHHHD

tLZHSB

RWI

Figure 13. AutoStore Enable/Disable Cycle

Address

CE

tSA

tRC

Address #1

tSA

tCW

OE

DQ (DATA)

tLZCE

tHA

tHA

tHZCE

tRC

Address #6

tCW

tHA

tHA

39

Note

tSS

t DELAY

Notes

37. The software sequence is clocked with CE controlled or OE controlled reads.

38. The six consecutive addresses must be read in the order listed in Table 2 on page 6. WE must be HIGH during all six consecutive cycles.

39. DQ output data at the sixth read may be invalid because the output is disabled at tDELAY time.

Document #: 001-42879 Rev. *K

Page 15 of 26

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