CY14B101LA-BA45XIT Просмотр технического описания (PDF) - Cypress Semiconductor
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CY14B101LA-BA45XIT Datasheet PDF : 30 Pages
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CY14B101LA
CY14B101NA
Hardware STORE Cycle
Over the Operating Range
Parameter
Description
tDHSB
tPHSB
tSS [49, 50]
HSB to output active time when write latch not set
Hardware STORE pulse width
Soft sequence processing time
20 ns
Min
Max
–
20
15
–
–
100
25 ns
Min
Max
–
25
15
–
–
100
45 ns
Unit
Min
Max
–
25
ns
15
–
ns
–
100 s
Switching Waveforms
Write latch set
HSB (IN)
tPHSB
HSB (OUT)
tDELAY
DQ (Data Out)
RWI
Write latch not set
tPHSB
HSB (IN)
HSB (OUT)
RWI
tDELAY
Figure 14. Hardware STORE Cycle [51]
tSTORE
tHHHD
tLZHSB
tDHSB
tDHSB
HSB pin is driven high to VCC only by Internal
100 kOhm resistor,
HSB driver is disabled
SRAM is disabled as long as HSB (IN) is driven low.
Address
CE
VCC
Figure 15. Soft Sequence Processing [49, 50]
Soft Sequence
tSS
Command
Address #1
tSA
Address #6
tCW
Soft Sequence
tSS
Command
Address #1
Address #6
tCW
Notes
49. This is the amount of time it takes to take action on a soft sequence command. VCC power must remain HIGH to effectively register command.
50. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command.
51. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.
Document Number: 001-42879 Rev. *P
Page 17 of 30
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