CXP86332 Просмотр технического описания (PDF) - Sony Semiconductor

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CXP86332

CMOS 8-bit Single Chip Microcomputer

Sony Semiconductor 

CXP86212/86216, CXP86324/86332, CXP86440/86448/86460

Absolute Maximum Ratings

(Vss = 0V reference)

Item

Symbol

Ratings

Unit

Remarks

Supply voltage

Input voltage

Output voltage

VDD

VIN

VOUT

–0.3 to +7.0

V

–0.3 to +7.0∗1

V

–0.3 to +7.0∗1

V

Medium drive output voltage VOUTP

–0.3 to +15.0

V

High level output current

IOH

–5

mA

High level total output current ∑IOH

–50

mA Total of all output pins

IOL

Low level output current

IOLC

15

mA

Ports excluding large current output

(value per pin)

20

mA

Large current output ports

(value per pin∗2)

Low level total output current ∑IOL

130

mA Total of all output pins

Operating temperature

Topr

–20 to +75

°C

Storage temperature

Tstg

–55 to +150

°C

1000

mW SDIP-64P-01

Allowable power dissipation

PD

600

mW QFP-64P-L01

380

mW LQFP-64P-L01

∗1 VIN and VOUT should not exceed VDD + 0.3 V.

∗2 The large current output port is Port C (PC6, PC7), Port D (PD) and Port F (PF).

Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should

be conducted under the recommended operating conditions. Exceeding those conditions may

adversely affect the reliability of the LSI.

Recommended Operating Conditions

(Vss = 0V reference)

Item

Symbol Min.

Max. Unit

Remarks

4.5

5.5

V

Guaranteed operation range for 1/2 and 1/4

frequency dividing modes

Supply voltage

VDD

3.5

5.5

V

Guaranteed operation range for 1/16 frequency

dividing mode or sleep

High level input

voltage

Low level input

voltage

VIH

VIHS

VIHEX

VIL

VILS

VILEX

2.7

5.5

V Guaranteed operation range for TEX mode

—

—

V Guaranteed data hold range for stop∗1

0.7VDD

VDD

V ∗2

0.8VDD

VDD

V ∗3

VDD – 0.4 VDD + 0.3 V EXTAL pin∗4, TEX pin∗5

0

0.3VDD V ∗2

0

0.2VDD V ∗3

–0.3

0.4

V EXTAL pin∗4, TEX pin∗5

Operating temperature Topr

–20

+75 °C

∗1 This device does not enter the STOP mode.

∗2 PA1 to 5, PB3 to 7, PC0 to PC5, PD2, PE0, PE1, PE3, PG3 to PG6, SCL0 to 1, SDA0 to 1 pins

∗3 VSYNC, HSYNC, INT2, SCK, SI, HS0, HS1, RMC, EC, INT0, INT1, RST pins

∗4 Specifies only during external clock input.

∗5 Specifies only during external event count input. – 12 –

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