CXA3197 Просмотр технического описания (PDF) - Sony Semiconductor

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CXA3197

10-bit 125MSPS D/A Converter

Sony Semiconductor 

CXA3197R

Notes on Use

• The CXA3197R has PECL and TTL input pins for the clock and reset inputs. When the clock is input at PECL

level, it is recommended to also input the reset signal at PECL level. Likewise, when the clock is input at TTL

level, it is recommended to also input the reset signal at TTL level.

• The input signal impedance should be properly matched to ensure the stable CXA3197R operation at high

speed.

Particularly when ringing appears in the input clock in the MUX.1A and MUX.1B modes, if this ringing

exceeds the clock input threshold value, the internal 1/2 frequency divider circuit may misoperate.

• All TTL input pins of the CXA3197R except for the PS pin go to High level when left open, and only the PS

pin goes to Low level when left open. Set the PS pin to High level to operate the IC.

When the PECL input pins are left open, the P (positive) side goes to High level and the N (negative) side

goes to Low level. The PECL input pins are complementary, so be sure to use the P and N sides together.

• When the clock and reset input signal level is TTL, ∗∗∗/T pins should be used and ∗∗∗/E pins left open. When

the clock and reset input signal level is PECL, ∗∗∗/E pins should be used and ∗∗∗/T pins left open.

• The power supply and grounding have a profound influence on converter characteristics. The power supply

and grounding method are particularly important during high-speed operation.

General points for caution are as follows.

— The ground pattern should be as wide as possible. It is recommended to make the power supply and

ground wider at an inner layer using a multi-layer board.

To prevent a DC offset from being generated between the analog and digital power supply patterns, it is

recommended to connect the patterns at one point via a ferrite-bead filter, etc.

— When using the CXA3197R with a single power supply, connect DGND1 and DGND2 to a common digital

ground, and AGND2 to an analog ground. Also, DVCC1 and DVCC2 should use a common digital power

supply, and AVCC2 should be connected to an analog power supply. AVCCO serves as the analog output

reference, so while it does not need to share the analog power supply, it should be used within the range

that satisfies the analog output compliance voltage.

— When using the CXA3197R with dual power supply, connect DGND1 and DVCC2 to the digital ground, and

AVCC2 to the analog ground. DVCC1 uses a positive digital power supply (+5V, typ.), DGND2 uses a

negative digital power supply (–5V, typ.), and AGND2 uses a negative analog power supply (–5V, typ.).

Like when using a single power supply, the AVCCO pin can be used within the range that satisfies the

analog output compliance voltage. However, connecting it to the analog ground and using the analog

ground as the reference for the analog output is recommended.

— Ground the power supply pins as close to each pin as possible with a 0.1µF or more ceramic chip

capacitor.

When using a single power supply, connect DVCC1 and DVCC2 to the digital ground, and AVCC2 and

AVCCO to the analog ground.

When using dual power supply, connect DVCC1 and DGND2 to the digital ground, and AGND2 to the

analog ground. In this case, when using AVCCO within the range that satisfies the compliance voltage, be

sure to also connect the AVCCO pin to the analog ground using a ceramic chip capacitor.

• The CXA3197R is designed with an analog output impedance of 50Ω. The analog outputs are wired with a

characteristic impedance of 50Ω, and waveforms free of reflection can be obtained by terminating the analog

outputs with 50Ω. Even when using only one of either AOUTP or AOUTN, if one analog output is terminated

with 50Ω, be sure to also terminate the other analog output with 50Ω. (See the Application Circuit.)

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