CXA1166K
Pin Description
Pin
No.
Symbol
I/O
Standard
voltage level
1 LINV
I
ECL
33 MINV
I
ECL
Equivalent circuit
DGND1
18
r
LINV
r
or 1
r
33
MINV
–1.3V
DVEE
r
8
28
Description
Polarity selection other than
MSB and overrange.
(Refer to the table of input
voltage vs. Digital output)
Low level is maintained with
left open.
Polarity selection for MSB
(Refer to the table of input
voltage vs. Digital output)
Low level is maintained with
left open.
64 VRT
65 VRTS
52 VRM
39 VRBS
40 VRB
I
0V
VRT 64
r2
r1
VRTS 65
r⁄2
O
0V
r
r3
I
VRB/2
VRM 25
r
r
O
–2V
r4
r ⁄2
VRBS 39
r5
I
–2V
VRB 40
Reference voltage
(Top) (0V typ.)
To
Comparator
Reference voltage sense
(Top)
Reference voltage mid-point.
Can be used for linearity
compensation.
Reference voltage sense
(Bottom)
Reference voltage (Bottom)
54
55
VIN1
49
50
VIN2
VIN1
54
55
VRTS
I
to
49
VRBS
50
VIN2
43, 48, 51, 53, 56, 61
AGND
To Comp
0 to 127
128 to 255
Analog input.
Pins 49, 50 and Pins 54, 55
should be connected
externally.
35 CLK
34 CLK
DGND1
I
ECL
18
CLK
35
CLK
34
I
ECL
rr
r
r
DVEE
8
28
rr
–4–
CLK input
Complementary CLK input.
ECL threshold potential
(–1.3V) is maintained with
left open.
The complementary input is
recommended for stable
operation at high speed
though the operation only
with the CLK input is
possible when the CLK
input is left open.