CS5571 Просмотр технического описания (PDF) - Cirrus Logic

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CS5571

±2.5 V / 5 V, 100 kSps, 16-bit, High-throughput ∆Σ ADC

Cirrus Logic 

3/25/08

10:56

CS5571

SWITCHING CHARACTERISTICS

TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%;

VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5%

Input levels: Logic 0 = 0V = Low; Logic 1 = VD+ = High; CL = 15 pF.

Parameter

Symbol Min

Typ

Max Unit

Master Clock Frequency

Internal Oscillator XIN

12

14

16

MHz

External Clock fclk

0.5

16

16.2 MHz

Master Clock Duty Cycle

40

-

60

%

Reset

RST Low Time

(Note 9) tres

1

-

-

µs

RST rising to RDY falling

Internal Oscillator twup

External Clock

-

120

-

µs

-

1536

- MCLKs

Conversion

CONV Pulse Width

tcpw

4

-

- MCLKs

BP/UP setup to CONV falling

(Note 10) tscn

0

-

-

ns

CONV low to start of conversion

tscn

-

-

2 MCLKs

Perform Single Conversion (CONV high before RDY falling)

tbus

20

-

- MCLKs

Conversion Time

(Note 11)

Start of Conversion to RDY falling tbuh

-

-

164 MCLKs

9. Reset must not be released until the power supplies and the voltage reference are within specification.

10. BP/UP can be changed coincident to CONV falling. BP/UP must remain stable until RDY falls.

11. If CONV is held low continuously, conversions occur every 160 MCLK cycles.

If RDY is tied to CONV, conversions will occur every 162 MCLKs.

If CONV is operated asynchronously to MCLK, a conversion may take up to 164 MCLKs.

RDY falls at the end of conversion.

6

DS768PP1

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