CAT5221(2013) Просмотр технического описания (PDF) - ON Semiconductor
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CAT5221 Datasheet PDF : 15 Pages
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CAT5221
between one of the four potentiometers and one of its
associated registers; or the transfer can occur between all
potentiometers and one associated register.
Four instructions require a two-byte sequence to
complete, as illustrated in Figure 10. These instructions
transfer data between the host/processor and the CAT5221;
either between the host and one of the data registers or
directly between the host and the Wiper Control Register.
These instructions are:
XFR Data Register to Wiper Control Register −
This transfers the contents of one specified Data
Register to the associated Wiper Control Register.
XFR Wiper Control Register to Data Register −
This transfers the contents of the specified Wiper
Control Register to the specified associated Data
Register.
Global XFR Data Register to Wiper Control
Register − This transfers the contents of all specified
Data Registers to the associated Wiper Control
Registers.
Global XFR Wiper Counter Register to Data
Register − This transfers the contents of all Wiper
Control Registers to the specified associated Data
Registers.
Increment/Decrement Command
The final command is Increment/Decrement (Figures 6
and 12). The Increment/Decrement command is different
from the other commands. Once the command is issued and
the CAT5221 has responded with an acknowledge, the
master can clock the selected wiper up and/or down in one
segment steps; thereby providing a fine tuning capability to
the host. For each SCL clock pulse (tHIGH) while SDA is
HIGH, the selected wiper will move one resistor segment
towards the RH terminal. Similarly, for each SCL clock
pulse while SDA is LOW, the selected wiper will move one
resistor segment towards the RL terminal.
See Instructions format for more detail.
SDA
0101
S ID3 ID2 ID1 ID0 A3 A2 A1 A0 A I3 I2 I1 I0 0 P0 R1 R0 A
T
C
C
S
T
A
K
KO
R Device ID
Internal
Instruction Pot/WCR Register
P
T
Address
Opcode Address Address
Figure 10. Two-byte Instruction Sequence
SDA
0 101
S
T
ID3 ID2 ID1 ID0 A3 A2 A1 A0
A
C
A
R
Device ID
T
Internal
K
Address
I3 I2 I1 I0 0 P0 R1 R0 A
C
K
Instruction Pot/WCR Data
Opcode Address Register
Address
D7 D6 D5 D4 D3 D2 D1 D0 A S
CT
WCR[7:0]
or
KO
P
Data Register D[7:0]
Figure 11. Three-byte Instruction Sequence
SDA
0 10 1
S ID3 ID2 ID1 ID0 A3 A2 A1 A0 A I3 I2 I1 I0 0 P0 R1 R0 A I I
T
C
CN N
A Device ID
R
T
Internal
Address
K
Instruction
Opcode
Pot/WCR Data K
Address Register
C
1
C
2
Address
Figure 12. Increment/Decrement Instruction Sequence
ID
NE
CC
n1
DS
ET
CO
nP
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10
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