C8051F121-GQ Просмотр технического описания (PDF) - Silicon Laboratories

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C8051F121-GQ

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F120/1/2/3/4/5/6/7

C8051F130/1/2/3

DOCUMENT CHANGE LIST

Revision 1.3 to Revision 1.4

• Added new paragraph tags: SFR Definition and JTAG Register Definition.

• Product Selection Guide Table 1.1: Added RoHS-compliant ordering information.

• Overview Chapter, Figure 1.8, “On-Chip Memory Map”: Corrected on-chip XRAM size to “8192 Bytes”.

• SAR8 Chapter: Table 7.1, “ADC2 Electrical Characteristics”: Track/Hold minimum spec corrected to

“300 ns”.

• SAR8 Chapter: Table 7.1, “ADC2 Electrical Characteristics”: Total Harmonic Distortion typical spec

corrected to “-51 dB”.

• Oscillators Chapter, Figure 14.1, “Oscillator Diagram”: Corrected location of IOSCEN arrow.

• CIP51 Chapter, Section 11.3: Added note describing EA change behavior when followed by single-

cycle instruction.

• CIP51 Chapter, Interrupt Summary Table: Added “SFRPAGE” column and SFRPAGE value for each

interrupt source.

• CIP-51 Chapter, Figure 11.2, “Memory Map”: Corrected on-chip XRAM size to “8192 Bytes”.

• Port I/O Chapter, Crossbar Priority Figures: Character formatting problem corrected.

• Port I/O Chapter, P7MDOUT Register Description: Removed references to UART and SMBus periph-

erals.

• Port I/O Chapter, P3MDOUT Register Description: Corrected text to read “P3MDOUT.[7:0]”.

• Timers Chapter: References to “TnCON” corrected to read “TMRnCN”.

• PCA0 Chapter, Section 24.1: Added note about PCA0CN Register and effects of read-modify-write

instructions on the CF bit.

Rev. 1.4

349

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