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производитель

C8051F043

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F040/1/2/3/4/5/6/7

VDD

VDD

VDD

DGND

DGND

DGND

AV+

AV+

AV+

AGND

AGND

AGND

TCK

TMS

TDI

TDO

/RST

MONEN

XTAL1

XTAL2

VREF

VREFD

DAC1

DAC0

VREF0

AIN0.0

AIN0.1

AIN0.2

AIN0.3

HVAIN+

HVAIN-

HVREF

HVCAP

Digital Power

8

Analog Power

0

5

JTAG Boundary Scan

1

Logic Debug HW

Reset

VDD

Monitor

WDT

C

External

Oscillator

Circuit

VREF

o

System

Clock

r

DAC1

Internal

e

(12-Bit)

Oscillator

DAC0

(12-Bit)

SFR Bus

Memories

64 kB

Flash

32x136

CANRAM

256 byte

RAM

4 kB

RAM

A

M

Prog

U

Gain

X

TEMP

SENSOR

HVAMP

ADC

100 ksps

(12 or 10-

Bit)

External Memory Data

Bus

A

M

8:2

U

X

UART0

UART1

SMBus

SPI Bus

PCA

Timers

0,1,2,3,4

Port

0,1,2,3

&4

Latches

CAN

2.0B

P0

Drv

C

R

P1

O

Drv

S

S

B

P2

Drv

A

R

P3

Drv

ADC

500 ksps

(8-Bit)

A

Prog

Gain

M 8:1

U

X

CP0

+

-

+

CP1

-

+

CP2

-

P2.6

P2.7

P2.2

P2.3

P2.4

P2.5

Port 4 <from crossbar>

Bus Control

Address [15:0]

Data [7:0]

Ctrl Latch

P5 Latch

Addr [15:8]

P6 Latch

Addr [7:0]

P7 Latch

Data Latch

P4

DRV

P5

DRV

P6

DRV

P7

DRV

P0.0

P0.7

P1.0

P1.7

P2.0

P2.7

P3.0

P3.7

CANTX

CANRX

VREF2

P4.0

P4.4

P4.5/ALE

P4.6/RD

P4.7/WR

P5.0/A8

P5.7/A51

P6.0/A0

P6.7/A7

P7.0/D0

P7.7/D7

Figure 1.1. C8051F040/2 Block Diagram

Rev. 1.5

21

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