BD8962MUVE2 Просмотр технического описания (PDF) - ROHM Semiconductor
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BD8962MUVE2 Datasheet PDF : 20 Pages
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BD8962MUV
Switching Regulator Efficiency
Efficiency ŋ may be expressed by the equation shown below:
η= VOUT×IOUT ×100[%]= POUT ×100[%]=
POUT
×100[%]
Vin×Iin
Pin
POUT+PDα
Datasheet
Efficiency may be improved by reducing the switching regulator power dissipation factors PDα as follows:
Dissipation factors:
1) ON resistance dissipation of inductor and FET：PD(I2R)
2) Gate charge/discharge dissipation：PD(Gate)
3) Switching dissipation：PD(SW)
4) ESR dissipation of capacitor：PD(ESR)
5) Operating current dissipation of IC：PD(IC)
1)PD(I2R)=IOUT2×(RCOIL+RON) (RCOIL[Ω]：DC resistance of inductor, RON[Ω]：ON resistance of FET, IOUT[A]：Output
current.)
2)PD(Gate)=Cgs×f×V (Cgs[F]：Gate capacitance of FET, f[H]：Switching frequency, V[V]：Gate driving voltage of FET)
Vin2×CRSS×IOUT×f
3)PD(SW)=
IDRIVE
(CRSS[F]：Reverse transfer capacitance of FET, IDRIVE[A]：Peak current of gate.)
4)PD(ESR)=IRMS2×ESR (IRMS[A]：Ripple current of capacitor, ESR[Ω]：Equivalent series resistance.)
5)PD(IC)=Vin×ICC (ICC[A]：Circuit current.)
Consideration on Permissible Dissipation and Heat Generation
As this IC functions with high efficiency without significant heat generation in most applications, no special
consideration is needed on permissible dissipation or heat generation. In case of extreme conditions,
however, including lower input voltage, higher output voltage, heavier load, and/or higher temperature, the
permissible dissipation and/or heat generation must be carefully considered.
For dissipation, only conduction losses due to DC resistance of inductor and ON resistance of FET are considered.
Because the conduction losses are considered to play the leading role among other dissipation mentioned above including
gate charge/discharge dissipation and switching dissipation.
4.0
①3.56W
3.0
2.0
① 4 layers (Copper foil area : 5505mm2)
copper foil in each layers.
θj-a=35.1℃/W
② 4 layers (Copper foil area : 10.29m2)
copper foil in each layers.
θj-a=103.3℃/W
③ 4 layers (Copper foil area : 10.29m2)
θj-a=178.6℃/W
④IC only.
θj-a=367.6℃/W
②1.21W
1.0
③0.70W
④0.34W
0
0 25 50
75 100105 125 150
Ambient temperature:Ta [℃]
Fig.25 Thermal derating curve
(VQFN020V4040)
P=IOUT2×RON
RON=D×RONP+(1-D)RONN
D：ON duty (=VOUT/VCC)
RONH：ON resistance of Highside MOS FET
RONL：ON resistance of Lowside MOS FET
IOUT：Output current
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TSZ22111･15･001
11/18
TSZ2201-0J3J0AJ00030-1-2
02.MAR.2012 Rev.001
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