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AT88SC1003-09PT

1K EEPROM–Security Logic with Three Application Zones

Atmel Corporation 

AT88SC1003

Device Functional Operation

Table 9. Device Functional Operation

Function

Operation Sequence

POR

OPERATION:

POR (power-on reset) is initiated as the device power supply ramps from 0V up to a valid operating voltage.

FUNCTION:

POR resets all flags, and the address is reset to “0”.

RESET

OPERATION:

With CLK low, a falling edge on the RST pin will reset the address counter to address 0.

FUNCTION:

The address is reset to “0”, and the first bit of the memory is driven by the AT88SC1003 on I/O after a reset. E1,

E2, and E3 are reset when the address is reset to “0”. The reset operation has no effect on any of the other flags

(SV, P1, P2, P3, R1, R2, R3).

ADDRESSING

OPERATION:

Addressing is handled by an internal address counter. The address is incremented on the falling edge of CLK.

Reset must be low while incrementing the address. The falling edge of reset clears the counter to address “0”.

FUNCTION:

Addressing of the AT88SC1003 is sequential. Specific bit addresses may be reached by completing a reset and

then clocking the device (INC/READ) until the desired address is reached. The AT88SC1003 will determine which

operations are allowed at specific address locations. These operations are specified in Table 6 and Table 7.

EXAMPLE:

To address the Issuer Zone (IZ), execute a reset operation, then clock the device 16 times. The device now

outputs the first bit of the IZ. After the address counter counts up to 1599, the next CLK pulse resets the address

to “0”.

READ

OPERATION:

RST and PGM pins must be low. If a read operation is allowed, the state of the memory bit being addressed is

output on the I/O pin. The I/O buffer is an open drain and the output of a logic “0”, which therefore causes the

device to pull the pin to ground. The output of a logic “1” causes the device to place the pin in a high impedance

state. Therefore, in order to sense a logic “1”, an external pullup must be placed between the I/O pin and VCC.

The address counter is incremented on the falling edge of CLK.

FUNCTION:

Non-application Zones:

As the address is incremented, the contents of the memory are read out on the I/O pin. The read operation is

inhibited for addresses where security prevents a read operation (see Table 6 and Table 7).

Application Zones:

The application zones can be read when: SV = “1” or R1(AZ1) / R2(AZ2) / R3(AZ3) = “1”

FUSE READ

OPERATION:

When the FUS pin is high, the state of the various fuses can be read when addressing the corresponding bits in

the memory.

FUNCTION:

To verify the state of the fuses.

15

2035B–SMEM–08/03

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