EDS2508APSA, EDS2516APSA
Pin Capacitance (TA = 25°C, VDD, VDDQ = 3.3V ± 0.3V)
Parameter
Symbol Pins
min.
Typ
max.
Unit
Input capacitance
CI1
CLK
2.0
—
CI2
Address, CKE, /CS, /RAS,
/CAS, /WE, DQM,
2.0
—
Data input/output capacitance CI/O
DQ
4
—
3.5
pF
3.8
pF
6.5
pF
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. Measurement condition: f = 1MHz, 1.4V bias, 200mV swing.
3. DQM = VIH to disable DOUT.
4. This parameter is sampled and not 100% tested.
Notes
1, 2, 4
1, 2, 4
1, 2, 3, 4
AC Characteristics (TA = 0 to +70°C, VDD, VDDQ = 3.3V ± 0.3V, VSS, VSSQ = 0V)
-7A
-75
Parameter
Symbol
min.
max.
min.
max.
Unit
System clock cycle time
tCK
7.5
—
7.5
—
ns
CLK high pulse width
tCH
2.5
—
2.5
—
ns
CLK low pulse width
tCL
2.5
—
2.5
—
ns
Access time from CLK
tAC
—
5.4
—
5.4
ns
Data-out hold time
tOH
3.0
—
3.0
—
ns
CLK to Data-out low impedance tLZ
1
—
1
—
ns
CLK to Data-out high impedance tHZ
—
5.4
—
5.4
ns
Input setup time
tSI
1.5
—
1.5
—
ns
Input hold time
tHI
0.8
—
0.8
—
ns
Ref/Active to Ref/Active command
period
Active to Precharge command
period
Active command to column
command (same bank)
Precharge to active command
period
Write recovery or data-in to
precharge lead time
tRC
tRAS
tRCD
tRP
tDPL
Last data into active latency
tDAL
Active (a) to Active (b) command
period
tRRD
60
—
67.5
—
ns
45
120000
45
120000
ns
15
—
20
—
ns
15
—
20
—
ns
15
—
15
—
ns
2CLK +
15ns
—
2CLK +
20ns
—
15
—
15
—
ns
Transition time (rise and fall)
tT
0.5
5
0.5
5
ns
Refresh period
(8192 refresh cycles)
tREF
—
64
—
64
ms
Notes: 1. AC measurement assumes tT = 0.5ns. Reference level for timing of input signals is 1.4V.
2. Access time is measured at 1.4V. Load condition is CL = 50pF.
3. tLZ (min.) defines the time at which the outputs achieves the low impedance state.
4. tHZ (max.) defines the time at which the outputs achieves the high impedance state.
Notes
1
1
1
1, 2
1, 2
1, 2, 3
1, 4
1
1
1
1
1
1
1
1
Data Sheet E0228E30 (Ver. 3.0)
6