EDS1232CABB Просмотр технического описания (PDF) - Elpida Memory, Inc

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Компоненты Описание

производитель

EDS1232CABB

128M bits SDRAM

Elpida Memory, Inc 

EDS1232CABB, EDS1232CATA

Bank active command interval

1. Same bank: The interval between the two bank active commands must be no less than tRC.

2. In the case of different bank active commands: The interval between the two bank active commands must be no

less than tRRD.

CLK

Command

ACT

ACT

Address

ROW

ROW

BS

Bank 0

Active

tRC

Bank Active to Bank Active for Same Bank

Bank 0

Active

CLK

Command

Address

ACT

ROW:0

ACT

ROW:1

BS

Bank 0

Active

tRRD

Bank 3

Active

Bank Active to Bank Active for Different Bank

Mode register set to Bank active command interval

The interval between setting the mode register and executing a bank active command must be no less than lMRD.

CLK

Command

MRS

ACT

Address

OPCODE

BS & ROW

IMRD

Mode

Register Set

Bank

Active

Mode register set to Bank active command interval

Preliminary Data Sheet E0247E40 (Ver. 4.0)

41

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