ADV7197KST Просмотр технического описания (PDF) - Analog Devices
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ADV7197KST Datasheet PDF : 20 Pages
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ADV7197
MODE REGISTER 4
MR4 (MR47–MR40)
(Address (SR4–SR0) = 04H)
Figure 19 shows the various operations under the control of
Mode Register 4.
MR4 BIT DESCRIPTION
Timing Reset (MR40)
Toggling MR40 from low to high and low again resets the inter-
nal horizontal and vertical timing counters.
MODE REGISTER 5
MR5 (MR57–MR50)
(Address (SR4-SR0) = 05H)
Figure 20 shows the various operations under the control of
Mode Register 5.
MR5 BIT DESCRIPTION
Reserved (MR50)
This bit is reserved for the revision code.
RGB Mode (MR51)
When RGB mode is enabled (MR51 = “1”) the ADV7197
accepts unsigned binary RGB data at its input port. This control
is also available in Async Timing Mode.
Sync on PrPb (MR52)
By default the color component output signals Pr, Pb do not
contain any horizontal sync pulses. They can be inserted when
MR52 = “1.”
This control is not available in RGB mode.
Color Output Swap (MR53)
By default DAC B is configured as the Pr output and DAC C
as the Pb output. In setting this bit to “1” the DAC outputs
can be swapped around so that DAC B outputs Pb and DAC C
outputs Pr. The table below demonstrates this in more detail.
This control is also available in RGB mode.
Reserved (MR54–MR57)
A “0” must be written to these bits.
Table II. Relationship Between Color Input Pixel Port, MR53
and DAC B, DAC C Outputs
In 4:4:4 Input Mode
Color Data
Input on Pins
Cr9–0
Cb/Cr9–0
Cr9–0
Cb/Cr9–0
MR53
0
0
1
1
Analog Output
Signal
DAC B
DAC C
DAC C
DAC B
In 4:2:2 Input Mode
Color Data
Input on Pins
Cr9–0
Cb/Cr9–0
Cb/Cr9–0
MR53
0 or 1
0
1
Analog Output
Signal
Not Operational
DAC C (Pb)
DAC C (Pr)
MR47
MR46
MR45
MR44
MR43
MR42
MR41
MR40
MR47–MR41
ZERO MUST BE
WRITTEN TO
THESE REGISTERS
Figure 19. Mode Register 4
TIMING RESET
MR40
MR57
MR56
MR55
MR54
MR53
MR52
MR51
MR50
MR57–MR54
ZERO MUST BE
WRITTEN TO
THESE BITS
SYNC ON PrPb
MR52
0
1
DISABLE
ENABLE
MR50
RESERVED FOR
REVISION CODE
COLOR OUTPUT
SWAP
MR53
0
DAC B = Pr
1
DAC C = Pr
RGB MODE
MR51
0
1
DISABLE
ENABLE
Figure 20. Mode Register 5
REV. 0
–15–
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