ADT7517ARQ Просмотр технического описания (PDF) - Analog Devices

Номер в каталоге

Компоненты Описание

производитель

ADT7517ARQ

SPI-/I2C-Compatible, Temperature Sensor, 4-Channel ADC and Quad Voltage Output

Analog Devices 

ADT7516/ADT7517/ADT7519

I2C Serial Interface

Like all I2C-compatible devices, the ADT7516/ADT7517/

ADT7519 have a 7-bit serial address. The four MSBs of this

address for the ADT7516/ADT7517/ADT7519 are set to 1001.

The three LSBs are set by Pin 11, ADD. The ADD pin can be

configured three ways to give three different address options:

low, floating, and high. Setting the ADD pin low gives a serial bus

address of 1001 000, leaving it floating gives the Address 1001 010,

and setting it high gives the Address 1001 011. The recommended

pull-up resistor value is 10 kΩ.

There is an enable/disable bit for the SMBus timeout. When this

is enabled, the SMBus times out after 25 ms of no activity. To

enable it, set Bit 6 of the Control Configuration 2 register. The

power-on default is with the SMBus timeout disabled.

The ADT7516/ADT7517/ADT7519 support SMBus packet

error checking (PEC), but its use is optional. It is triggered by

supplying the extra clocks for the PEC byte. The PEC is

calculated using CRC-8. The frame clock sequence (FCS)

conforms to CRC-8 by the polynomial

C(x) = x8 + x2 + x1 + 1

Consult the SMBus specification for more information.

The serial bus protocol operates as follows:

1. The master initiates a data transfer by establishing a start

condition, defined as a high to low transition on the serial

data line (SDA) while the serial clock line (SCL) remains

high. This indicates that an address/data stream follows.

All slave peripherals connected to the serial bus respond to

the start condition and shift in the next eight bits,

consisting of a 7-bit address (MSB first) plus a R/W bit; this

determines the direction of the data transfer, that is,

whether data is written to or read from the slave device.

The peripheral whose address corresponds to the

transmitted address responds by pulling the data line low

during the low period before the ninth clock pulse, known

as the acknowledge bit. All other devices on the bus now

remain idle while the selected device waits for data to be

read from or written to it. If the R/W bit is 0, the master

writes to the slave device. If the R/W bit is 1, the master

reads from the slave device.

1

9

SCL

2. Data is sent over the serial bus in sequences of nine clock

pulses: eight bits of data followed by an acknowledge bit

from the receiver of data. Transitions on the data line must

occur during the low period of the clock signal and remain

stable during the high period, because a low to high

transition when the clock is high can be interpreted as a

stop signal.

3. When all data bytes have been read or written, stop

conditions are established. In write mode, the master pulls

the data line high during the 10th clock pulse to assert a

stop condition. In read mode, the master device pulls the

data line high during the low period before the ninth clock

pulse. This is known as no acknowledge. The master then

takes the data line low during the low period before the 10th

clock pulse, and then high during the 10th clock pulse to

assert a stop condition.

Any number of bytes of data can be transferred over the serial

bus in one operation, but it is not possible to mix read and write

in one operation because the type of operation is determined at

the beginning and cannot subsequently be changed without

starting a new operation.

The I2C address set up by the ADD pin is not latched by the

device until after this address has been sent twice. On the eighth

SCL cycle of the second valid communication, the serial bus

address is latched in. This is the SCL cycle directly after the

device has seen its own I2C serial bus address. Any subsequent

changes on this pin have no effect on the I2C serial bus address.

Writing to the ADT7516/ADT7517/ADT7519

Depending on the register being written to, there are two different

writes for the ADT7516/ADT7517/ADT7519. It is not possible

to do a block write to this part, that is, no I2C auto-increment.

Writing to the Address Pointer Register for a

Subsequent Read

To read data from a particular register, the address pointer

register must contain the address of that register. If it does not,

the correct address must be written to the address pointer

register by performing a single-byte write operation, as shown

in Figure 60. The write operation consists of the serial bus

address followed by the address pointer byte. No data is written

to any of the data registers. A read operation is then performed

to read the register.

1

9

SDA

1

START BY

MASTER

0

0

1

A2 A1 A0 R/W

P7 P6 P5 P4 P3 P2 P1 P0

ACK. BY

ADT7516/ADT7517/ADT7519

ACK. BY STOP BY

ADT7516/ADT7517/ADT7519 MASTER

FRAME 1

SERIAL BUS ADDRESS BYTE

FRAME 2

ADDRESS POINTER REGISTER BYTE

Figure 60. I2C—Writing to the Address Pointer Register to Select a Register for a Subsequent Read Operation

Rev. B | Page 38 of 44

Share Link: