ADT7516ARQ(RevA) Просмотр технического описания (PDF) - Analog Devices

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ADT7516ARQ
(Rev.:RevA)

SPI/I2C Compatible, Temperature Sensor, 4-Channel ADC and Quad Voltage Output DAC

Analog Devices 

ADT7516/ADT7517/ADT7519

Analog Input ESD Protection

Figure 52 shows the input structure on any of the analog input

pins that provides ESD protection. The diode provides the main

ESD protection for the analog inputs. Care must be taken that

the analog input signal never drops below the GND rail by

more than 200 mV. If this happens, the diode will become

forward-biased and start conducting current into the substrate.

The 4 pF capacitor is the typical pin capacitance and the resistor

is a lumped component made up of the on resistance of the

multiplexer switch.

100Ω

AIN

4pF

Figure 52. Equivalent Analog Input ESD Circuit

AIN Interrupts

The measured results from the AIN inputs are compared with

the AIN VHIGH (greater than comparison) and VLOW (less than or

equal to comparison) limits. An interrupt occurs if the AIN

inputs exceed or equal the limit registers. These voltage limits

are stored in on-chip registers. Note that the limit registers are 8

bits long while the AIN conversion result is 10 bits long. If the

voltage limits are not masked out, then any out-of-limit com-

parisons generate flags that are stored in the Interrupt Status 1

register (Address = 00h) and one or more out-of-limit results

will cause the INT/INT output to pull either high or low

depending on the output polarity setting. It is good design

practice to mask out interrupts for channels that are of no

concern to the application. Figure 53 shows the interrupt

structure for the ADT7516/ ADT7517/ADT7519. It gives a

block diagram representation of how the various measurement

channels affect the INT/INT pin.

S/W RESET

∗ Upper deadband has been reached. DAC output is not capable of increasing.

See Figure 9.

INTERRUPT

STATUS

REGISTER

(TEMP AND

AIN1 TO AIN4)

WATCHDOG

LIMIT

COMPARISONS

INTERRUPT

STATUS

REGISTER 2

(VDD)

INTERNAL

TEMP

EXTERNAL

TEMP

INTERRUPT

MASK

REGISTERS

VDD

DIODE

FAULT

AIN1–AIN4

INT/INT

(LATCHED OUTPUT)

READ RESET

CONTROL

CONFIGURATION

REGISTER 1

INT/INT

ENABLE BIT

Figure 53. ADT7516/ADT7517/ADT7519 Interrupt Structure

Rev. A | Page 24 of 44

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