ADSP-21469KBZ-ENG2 Просмотр технического описания (PDF) - Analog Devices

Номер в каталоге

Компоненты Описание

производитель

ADSP-21469KBZ-ENG2

SHARC Processor

Analog Devices 

ADSP-21469/ADSP-21469W

Preliminary Technical Data

PIN FUNCTION DESCRIPTIONS

The following symbols appear in the Type column of Table 6:

A = asynchronous, I = input, O = output, S = synchronous,

(A/D) = active drive, (O/D) = open drain, and T = three-state,

(pd) = pull-down resistor, (pu) = pull-up resistor.

Table 6. Pin List

Name

AMI_ADDR23–0

AMI_DATA7–0

DAI _P20–1

DPI _P14–1

AMI_ACK

AMI_RD

AMI_WR

DDR2_ADDR15-0

DDR2_BA2-0

DDR2_CAS

State

During

and After

Type

O/T

LVTTL SSTL18 Reset Description

3

High-Z/ External Address. The ADSP-21469 outputs addresses for external memory

driven low and peripherals on these pins. The data pins can be multiplexed to support

(boot)

the PDAP (I) and PWM (O). After reset, all AMI_ADDR23-0 pins are in EMIF mode

and FLAG(0-3) pins will be in FLAGS mode (default). When configured in the

IDP_PDAP_CTL register, IDP channel 0 scans the AMI_ADDR23–0 pins for

parallel input data.

I/O/T

3

High-Z External Data. The data pins can be multiplexed to support the external

memory interface data (I/O), the PDAP (I), FLAGS (I/O) and PWM (O). After reset,

all AMI_DATA pins are in EMIF mode and FLAG(0-3) pins will be in FLAGS mode

I/O with fixed weak 3

High-Z

(default).

Digital Applications Interface Pins. These pins provide the physical

pull-up on input

path 1, 2

interface to the DAI SRU. The DAI SRU configuration registers define the com-

bination of on-chip audiocentric peripheral inputs or outputs connected to

the pin and to the pin’s output enable. The configuration registers of these

peripherals then determine the exact behavior of the pin. Any input or output

signal present in the DAI SRU may be routed to any of these pins. The DAI SRU

provides the connection from the serial ports, the S/PDIF module, input data

I/O with fixed weak 3

High-Z

ports (2), and the precision clock generators (4), to the DAI_P20–1 pins.

Digital Peripheral Interface. These pins provide the physical interface to the

pull-up only on

input path1, 2

DPI SRU. The DPI SRU configuration registers define the combination of on-

chip peripheral inputs or outputs connected to the pin and to the pin’s output

enable. The configuration registers of these peripherals then determines the

exact behavior of the pin. Any input or output signal present in the DPI SRU

may be routed to any of these pins. The DPI SRU provides the connection from

the timers (2), SPIs (2), UART (1), flags (12), and general-purpose I/O (9) to the

I (pu)

3

DPI_P14–1 pins.

Memory Acknowledge (AMI_ACK). External devices can deassert AMI_ACK

(low) to add wait states to an external memory access. AMI_ACK is used by I/O

devices, memory controllers, or other peripherals to hold off completion of

an external memory access.

O/T

3

High-Z AMI Port Read Enable. AMI_RD is asserted whenever the ADSP-21469 reads

a word from external memory. AMI_RD has fixed internal pull-up resistor1, 2.

O/T

3

High-Z External Port Write Enable. AMI_WR is asserted when the ADSP-21469

writes a word to external memory. AMI_WR has fixed internal pull-up resistor1,

2.

O/T

3

High-Z/ DDR2 Address pins. DDR2 address pins.

Driven low

O/T

3

High-Z/ DDR2 Bank Address Input pins. Define which bank an ACTIVATE,

Driven low READ, WRITE, or PRECHARGE command is being applied. BA2–0

define which mode register including MR, EMR, EMR(2), and

EMR(3) is loaded during the LOAD MODE command.

O/T

3

High-Z/ DDR2 Column Address Strobe. Connect to DDR2_CAS pin, in conjunction

Driven with other DDR2 command pins, defines the operation for the DDR2 to

high

perform.

Rev. PrB | Page 12 of 56 | November 2008

Share Link: